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5.2 VIA VT8372 North Bridge
CPU Interface
Signal Name Pin # I/O Signal Description
CFWDRST D14 O CLK Forward Reset.Reset the clock forward circuitry for the
Athlon .interface.
CONNECT C14 O Connect.Used for power anagement and CLK-forward initialization at
reset.
PROCRDY E14 I Processor Ready.Used for power anagement and clock-forward
initialization at reset.
AIN[14-2]# (see pin O Host CPU Address /Command Output.Unidirectional syste address
list) /com and interface to the processor from the system controller.It is
used to transfer probes or data ovement com ands into the processor
during PCI-to-DRAM cycles to snoop the CPU internal Cache.
AIN[14:2]#is skew-aligned with the forward clock,AINCLK#
AINCLK# B15 O Host CPU Address Output Clock.Single-ended forwarded clock for
the AIN[14:2]# bus that is driven by the syste controller.Both rising
and falling edges are used to transfer addresses or com ands to the
processor.
AOUT[14-2]# (see pin I Host CPU Address Input.Unidirectional system address /command
list) interface from the processor to the system controller.It is used to
transfer processor com ands or probes responses to the syste
controller.AOUT[14:2]# is skew-aligned with the forward clock,
V-Link Interface
AOUTCLK#
Signal Name Pin # I/O Signal Description
AOUTCLK# R25 I Host CPU Address Input Clock.Single-ended forwarded clock for the
VAD7, AC1 IO Address/Data Bus. SB
AOUT[14:bus that is driven by the processor.Both rising and falling
Strap Function Setting (L=strap low,H=strap high) Register Pin
edges are used to transfer com ands or probe responses. VAD6 Auto-Configure L=Disable (use on-chip defaults) SDA2
VAD6 /strap AB4 IO
D[63-0]# see pin IO Host CPU Data.Bi-directional interface between the processor and the H=Enable (get from ROM)
list) system controller for data movement. D[63:0]#bus is skew-aligned
VAD5 /strap, Y2 IO VAD5 CPU Clock Divide Bit-3 (see register description) Rx97[6] SDA1
with either the DICLK[3:0]#or DOCLK[3:0]#forward clocks.
VAD4 /strap, AC2 IO VAD4 CPU Clock Divide Bit-2 (see register description) Rx97[5] SDA0
DICLK[3-0]# L24,G23O Host CPU Data Input Clock. Single-ended forwarded clocks for the
VAD3 /strap, Y1 IO VAD3 CPU Clock Divide Bit-1 (see register description) Rx97[4] SA19
, D[63:0]#bus, driven by the syste controller to the processor.Each
VAD2 /strap, AA4 IO VAD2 CPU Clock Divide Bit-0 (see register description) Rx97[3] SA18
A24,A116-bit data word is skew-aligned with one of these clocks.Both rising
VAD1 /strap, W5 IO VAD1 FSB Clock Speed Msb LL=66,LH=100, SA17
9 and falling edges are used to transfer data to the pocessor.
VAD0 /strap W4 IO VAD0 FSB Clock Speed Lsb HL=HH=133 MHz SA16
DOCLK[3-0]L22,F23I Host CPU Data Output Clock.Single-ended forwarded clocks for the
VBE# Y3 IO Byte Enable.
# , D[63:0]#bus, driven by the processor to the system controller.Each
B24,C19 16-bit data word is skew-aligned with one of these clocks.Both rising VUPCMD Y4 I Command from Client-to-Host.
and falling edges are used to transfer data to the system controller.
VUPSTB AA1 I Strobe from Client-to-Host.
DINVAL# E13 O HostCPUDataReadInVald.Driven by the syste controller to control the
VUPSTB# AA2 I Complement Strobe from Client-to-Host.
flow of data into the processor.DINVAL#can be used to introduce an
arbitrary number of cycles between octawords into the processor. VDNCMD AB3 O Command from Host-to-Client.
The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout VDNSTB AB1 O Strobe from Host-to-Client.
shown) as a guide for PCB component placement. Other PCB layouts (AT, LPX, and NLX) were also
VDNSTB# AB2 O Complement Strobe from Host-to-Client.
considered and can typically follow the same general component placement.
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