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5.3 Intel 82801DBM I/O Controller Hub 4 Mobile-4
IDE Interface Signals (Continued) LPC Interface Signals
Signal Name Type Description Signal Name Type Description
PIORDY#/ I Primary and Secondary I/O Channel Ready (PIO): This signal LAD[3:0]/ I/O LPC Multiplexed Command, Address, Data: For the LAD[3:0]
(PDRSTB/PWDMAwill keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# FWH[3:0] signals, internal pull-ups are provided.
RDY#) or SDIOW# on writes) longer than the minimum width. It adds wait LFRAME#/ O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an
states to PIO transfers. FWH[4] abort.
SIORDY#/ Primary and Secondary Disk Read Strobe (Ultra DMA Reads from LDRQ[1:0]# I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used
Disk): When reading from disk, the ICH4 latches data on rising and to request DMA or bus master access. These signals are typically
(SDRSTB/SWDMAfalling edges of this signal from the disk. connected to an external Super I/O device. An internal pull-up
RDY#)
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to resistor is provided on these signals.
Disk): When writing to disk, this is de-asserted by the disk to pause
burst data transfers.
USB Interface Signals
Signal Name Type Description
Interrupt Signals
Signal Name Type Description USBP0P, I/O Universal Serial Bus Port 1:0 Differential: These differential
USBP0N, pairs are used to transmit data/address/command signals for ports 0
SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt USBP1P, and 1. These ports can be routed to USB UHCI Controller #1 or the
protocol. USBP1N USB EHCI Controller.
PIRQ[D:A]# I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals NOTE: No external resistors are required on these signals. The
can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as ICH4 integrates 15 k . pull-downs and provides an output driver
described in the Interrupt Steering section. Each PIRQx# line has a impedance of 45 . which requires no external series resistor
separate Route Control Register. USBP2P, I/O Universal Serial Bus Port 3:2 Differential: These differential
In APIC mode, these signals are connected to the internal I/O APIC USBP2N, pairs are used to transmit data/address/command signals for ports 2
in the following fashion: PIRQ[A]# is connected to IRQ16, USBP3P, and 3. These ports can be routed to USB UHCI Controller #2 or the
PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. USBP3N USB EHCI Controller.
This frees the legacy interrupts. NOTE: No external resistors are required on these signals. The
PIRQ[H:E]#/ I/OD PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals ICH4 integrates 15 k . pull-downs and provides an output driver
GPIO[5:2] can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as impedance of 45 . which requires no external series resistor.
described in the Interrupt Steering section. Each PIRQx# line has a USBP4P, I/O Universal Serial Bus Port 5:4 Differential: These differential
separate Route Control Register. USBP4N, pairs are used to transmit data/address/command signals for ports 4
In APIC mode, these signals are connected to the internal I/O APIC USBP5P, and 5. These ports can be routed to USB UHCI Controller #3 or the
in the following fashion: PIRQ[E]# is connected to IRQ20, USBP4N USB EHCI Controller
PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. NOTE: No external resistors are required on these signals. The
This frees the legacy interrupts. If not needed for interrupts, these ICH4 integrates 15 k . pull-downs and provides an output driver
signals can be used as GPIO. impedance of 45 . which requires no external series resistor
IRQ[14:15] I Interrupt Request 14:15: These interrupt inputs are connected to OC[5:0]# I/O Overcurrent Indicators: These signals set corresponding bits in
the IDE drives. IRQ14 is used by the drives connected to the the USB controllers to indicate that an overcurrent condition has
Primary controller and IRQ15 is used by the drives connected to the occurred.
Secondary controller. USBRBIAS O USB Resistor Bias: Analog connection point for an external
APICCLK I APIC Clock: This clock operates up to 33.33 MHz. resistor to ground. USBRBIAS should be connected to
APICD[1:0] I/OD APIC Data: These bi-directional open drain signals are used to USBRBIAS# as close to the resistor as possible.
send and receive data over the APIC bus. As inputs the data is valid USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an
on the rising edge of APICCLK. As outputs, new data is driven external resistor to ground. USBRBIAS# should be connected to
from the rising edge of the APICCLK. USBRBIAS as close to the resistor as possible.
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