8677 8677 N/B MAINTENANCEN/B MAINTENANCE
5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Signal Description
Pin Name Type/No. Description Pin Name Type/No.Description
A[35:3]# Input/ A[35:3]# (Address) define a 236-byte physical memory address BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the system
Output space. In subphase 1 of the address phase, these pins transmit the bus frequency. All processor system bus agents must receive
address of a transaction. In sub-phase 2, these pins transmit these signals to drive their outputs and latch their inputs.
transaction type information. These signals must connect the All external timing parameters are specified with respect to the
appropriate pins of all agents on the Mobile Intel Pentium 4 rising edge of BCLK0 crossing VCROSS.
Processor-M system bus. A[35:3]# are protected by parity signals BINIT# Input/ BINIT# (Bus Initialization) may be observed and driven by all
AP[1:0]#. A[35:3]# are source synchronous signals and are latched Output processor system bus agents and if used, must connect the appropriate
into the receiving buffers by ADSTB[1:0]#. pins of all such agents. If the BINIT# driver is enabled during
On the active-to-inactive transition of RESET#, the processor samples power-on configuration, BINIT# is asserted to signal any bus
a subset of the A[35:3]# pins to determine power-on configuration. condition that prevents reliable future operation.
A20M# Input If A20M# (Address-20 Mask) is asserted, the processor masks If BINIT# observation is enabled during power-on configuration, and
physical address bit 20 (A20#) before looking up a line in any internal BINIT# is sampled asserted, symmetric agents reset their bus LOCK#
cache and before driving a read/write transaction on the bus.Asserting activity and bus request arbitration state machines. The bus agents do
A20M# emulates the 8086 processor's address wrap-around at the not reset their IOQ and transaction tracking state machines upon
1-Mbyte boundary. Assertion of A20M# is only supported in real observation of BINIT# activation. Once the BINIT# assertion has
mode. been observed, the bus agents will re-arbitrate for the system bus and
A20M# is an asynchronous signal. However, to ensure recognition of attempt completion of their bus queue and IOQ entries.
this signal following an Input/Output write instruction, it must be If BINIT# observation is disabled during power-on configuration, a
valid along with the TRDY# assertion of the corresponding central agent may handle an assertion of BINIT# as appropriate to the
Input/Output Write bus transaction. error handling architecture of the system.
ADS# Input/ Output ADS# (Address Strobe) is asserted to indicate the validity of the BNR# Input/ BNR# (Block Next Request) is used to assert a bus stall by any bus
transaction Output agent who is unable to accept new bus transactions. During a bus
ADSTB[1:0]# Input/ Address strobes are used to latch A[35:3]# and REQ[4:0]# on their stall, the current bus owner cannot issue any new transactions.
Output rising and falling edges. Strobes are associated with signals as shown BPM[5:0]# Input/ BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
below. Output monitor signals.
Signals Associated Strobe They are outputs from the processor which indicate the status of
REQ[4:0]#, A[16:3]# ADSTB0# breakpoints and programmable counters used for monitoring
A[35:17]# ADSTB1# processor performance. BPM[5:0]# should connect the appropriate
AP[1:0]# Input/ AP[1:0]# (Address Parity) are driven by the request initiator along pins of all Mobile Intel Pentium 4 Processor-M system bus agents.
Output with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A BPM4# provides PRDY# (Probe Ready) functionality for the TAP
correct parity signal is high if an even number of covered signals are port. PRDY# is a processor output used by debug tools to determine
low and low if an odd number of covered signals are low. This allows processor debug readiness.
parity to be high when all the covered signals are high. BPM5# provides PREQ# (Probe Request) functionality for the TAP
AP[1:0]# should connect the appropriate pins of all Mobile Intel port. PREQ# is used by debug tools to request debug operation of the
Pentium 4 Processor-M system bus agents. The following table processor.
defines the coverage model of these signals. Please refer to the Mobile Intel. Pentium. 4 Processor-M and Intel.
Request Signals subphase 1 subphase 2 845MP/845MZ Chipset Platform Design Guide and ITP700 Debug
A[35:24]# AP0# AP1# Port Design Guide for more detailed information.
These signals do not have on-die termination and must be
A[23:3]# AP1# AP0#
terminated on the system board.
REQ[4:0]# AP1# AP0#
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