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CHASSIS
12.5. FLASH (IC 314)
12.5.1. General Description
The MT28F128J3 is a nonvolatile, electrically block-erasable (Flash), programmable memory containing 134,217,728
bits organized as 16,777,218 bytes (8 bits) or 8,388,608 words (16 bits). This 128Mb device is organized as one
hundred twenty-eight 128KB erase blocks.
The MT28F640J3 contains 67,108,864 bits organized as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits). This
64Mb device is organized as sixty-four 128KB erase blocks.
Similarly, the MT28F320J3 contains 33,554,432 bits organized as 4,194,304 bytes (8 bits) or 2,097,152 words (16 bits).
This 32Mb device is organized as thirty-two 128KB erase blocks.
These three devices feature in-system block locking. They also have common Flash interface (CFI) that permits software
algorithms to be used for entire families of devices. The software is device-independent, JEDEC ID-independent with
forward and backward compatibility.
Additionally, the scalable command set (SCS) allows a single, simple software driver in all host systems to work with all
SCS-compliant Flash memory devices. The SCS provides the fastest system/device data transfer rates and minimizes
the device and system-level implementation costs.
To optimize the processor-memory interface, the device accommodates VPEN, which is switchable during block erase,
program, or lock bit configuration, or hard-wired to VCC, depending on the application. VPEN is treated as an input pin
to enable erasing, programming, and block locking. When VPEN is lower than the VCC lockout voltage (VLKO), all
program functions are disabled. Block erase suspend mode enables the user to stop block erase to read data from or
program data to any other blocks. Similarly, program suspend mode enables the user to suspend programming to read
data or execute code from any unsuspended blocks.
VPEN serves as an input with 2.7V, 3.3V, or 5V for application programming. VPEN in this Q-Flash _ family can provide
data protection when connected to ground. This pin also enables program or erase lockout during power transition.
Micron?s even-sectored Q-Flash devices offer individual block locking that can lock and unlock a block using the sector
lock bits command sequence.
Status (STS) is a logic signal output that gives an additional indicator of the internal state machine (ISM) activity by
providing a hardware signal of both status and status masking. This status indicator minimizes central processing unit
(CPU) overhead and system power consumption. In the default mode, STS acts as an RY/BY# pin. When LOW, STS
indicates that the ISM is performing a block erase, program, or lock bit configuration. When HIGH, STS indicates that
the ISM is ready for a new command.
Three chip enable (CE) pins are used for enabling and disabling the device by activating the device?s control logic, input
buffer, decoders, and sense amplifiers.
BYTE# enables the device to be used in x8 or x16 read/write mode; BYTE# = 0 selects an 8-bit mode, with address A0
selecting between the LOW and HIGH byte, while BYTE# = 1 selects a 16-bit mode. When BYTE# = 1, A1 becomes the
lowest-order address line with A0 being a no connect.
RP# is used to reset the device. When the device is disabled and RP# is at Vcc, the standby mode is enabled. A reset
time (t RWH) is required after RP# switches HIGH until outputs are valid. Likewise, the device has a wake time (t RS)
from RP# high until writes to the command user interface (CUI) are recognized. When RP# is at GND, it provides write
protection, resets the ISM, and clears the status register.
A variant of the MT28F320J3 also supports the new security block lock feature for additional code security. This feature
provides an OTP function for the device. (Contact factory for availability.)
The MT28F320J3 and the MT28F640J3 are manufactured using the 0.18?m process technology, and the MT28F128J3
is manufactured using the 0.15?m process technology.
12.5.2. Features
? x8/x16 organization
? One hundred twenty-eight 128KB erase blocks (128Mb)
Sixty-four 128KB erase blocks (64Mb)
Thirty-two 128KB erase blocks (32Mb)
?VCC, VCCQ, and VPEN voltages:
2.7V to 3.6V VCC operation
2.7V to 3.6V, or 5V VPEN application programming
? Interface Asynchronous Page Mode Reads:
150ns/25ns or 120ns/25ns read access time (128Mb)
120ns/25ns or 115ns/25ns read access time (64Mb)
110ns/25ns read access time (32Mb)
? Manufacturing ID (ManID)
19 |
ACEC
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