IC
23. BPHN out BURST PHASE-N output46.DLB inDELAY BURST input
24. BPHP out BURST PHASE-P output47.ADB inADVANCE BURST input
These are the outputs of the phase comparatorThese burst signals are used for phase
between the DLB(pin 46) /ADB(pin 47) inputs andcomparison with the internal SC.
the internal SC that is equivalent to the FSCBThe usual connection is as follows:
(pin 7) output.
The PDIH(pin 55) input inhibits the BPHN andCXD1312Q
BPHP outputs.47ADB
BPHN/BPHP
PDIH48REFB
OUTPUTS
(0) INHIBITBURST46DLB
DELAYDELAY
1ENABLE
25. GNDGND
26. VDD1+5V input48. REFB inREFERENCE BURST input
REFB is used for resetting the divide-by-8
27. PH5 inDELAY CONTROL INPUT FOR RZ1counter. RSIH(pin 51) inhibits the resetting
28. PH6 inDELAY CONTROL INPUT FOR RZ1as follows:
29. PH7 inDELAY CONTROL INPUT FOR RZ1
30. PH8 inDELAY CONTROL INPUT FOR RZ1RESET BY
31. PH9 inDELAY CONTROL INPUT FOR RZ1RSIH
32. PH10 inDELAY CONTROL INPUT FOR RZ1BY REFB
These inputs control the delay time of the RZ1(0)INHIBIT
(pin 6) output. See the description of PH0(pin1ENABLE
18) input.
49. LALTI in PAL PULSE input
33. NICK inNI CLOCK inputThe PAL pulse should be input to this terminal
NICK is the clock pulse to generate the NIfor the PAL system, but this terminal should be
(normal/invert) pulse to be used internally.kept open for the NTSC system.
Usually, CNTH(pin 63) for the NTSC system or
LALT(pin 13) for the PAL system is input to50. FLDI inPAL FIELD PULSE input
this terminal.Phase alternating pulse by field.
The rising edge is active.The FLDO(pin 54) output is usually input to this
terminal for the PAL system, but this terminal
34. SHIH inMODE SELECT (COLOR FRAMING DET./RZ GEN) inputshould be kept open for the NTSC system.
35. CFEN inMODE SELECT (COLOR FRAMING DET./RZ GEN) input
36. CFIH inMODE SELECT (COLOR FRAMING DET./RZ GEN) input51. RSIH inRESET INHIBIT input
These inputs set CXD1312Q to the color framingThis signal inhibits for the REFB(pin 48) input
detector mode or the read zero generator modeto reset the divide-by-8 counter of 8FSC(pin 15)
as follows:input.
See the description of the REFB(pin 48) input.
SHIH CFEN CFIHMODE52. SY1 inROUGH SYNC PULSE input (negative pulse)
0(0)1COLOR FRAMING DETECTORVR(pin 1) , CP1(pin 59) , CP2(pin 60) and the
internal gate pulse are derived from SY1.
(1)(0)(0) RZ GENERATOR
53. SY2 inSYNC PULSE input (negative pulse)
37. M6 inSIGNAL SYSTEM SELECT inputThis sync pulse generates GH(pin 61) , and GH is
Set M5(pin 45) and M6 as follows according asinput to the SC-H phase detection circuit. See
the video signal to be used.the description of DLH(pin 39) and ADH(pin 40).
54. FLDO out FIELD PULSE outputMODE & VIDEO SIGNAL M5M6
Phase altering pulse by field.
TEST00
4FSC/FH=909 : PALM0(1)55. PDIH inBPHN/BPHP OUTPUT INHIBIT input
This signal inhibits the BPHN(pin 23) and BPHP
4FSC/FH=910 : NTSC (1)0(pin 24) outputs. See the description of BPHN
4FSC/FH=1135: PAL(1) (1)and BPHP.
38.CFI inCOLOR FRAME PULSE input56.HCK innH CLOCK input
This pulse is used for resetting the internalThe frequency of the HCK input has the
LALT signal in the RZ GENERATOR mode.specified relation with that of the H sync
signal that composes the SY2(pin 53) input. See
39.DLH inDELAY H inputthe description of the M1(pin 14) input.
40.ADH inADVANCE H input
These H signals are used for the SC-H phase57.GNDGND
detection. The SC-H phase detector outputs58.VDD2+5V input
ADV(pin 11) and WIN (pin 12) according as the
phase relation between DLH/ADH and the internal59.CP1 outLEADING EDGE OF SY1(pin 52) output
SC that is equivalent to FSC(pin 8).60.CP2 outTRAILING EDGE OF SY1(pin 52) output
If the internal SC is between ADH and DLH, the
WIN output goes to LOW.61.GH outGATED H PULSE output
If the internal SC is in advance of ADH, the62.HR outH PULSE output
ADV output goes to LOW.GH and HR are derived from the SY2(pin 53) sync
The usual connection is as follows:pulse input. Both signals consist of H pulses
but not of a half H pulse.
CXD1312QGH is processed by the noise eliminator and
loses nine pulses in the V sync interval.
DELAYDELAY61GH63.CNTH outCOUNT H output
CNTH is a H pulse signal that is divided from
40ADHthe HCK(pin 56) input . the divider is reset by
41REFHthe SY1(pin 52) input.
39DLHSee the description of the M1(pin 14) input.
64.SABS outTEST output
41. REFH inREFERENCE H PULSE input
REFH is used for the color framing detector and
the RZ generator. GH(pin 61) or HR(pin 62) is
usually input to this terminal.
42. GNDGND
43. SCH outSC-H PHASE output
This signal shows the phase difference between
REFH(pin 41) and internal SC. When they are in
phase, the SCH output is as folows:
H
Hi-zHi-z
L1
2Fsc
44. SCR inDIRECT RESET INPUT FOR DIVIDE-BY-8 COUNTER
This signal resets the divide-by-8 counter of
8FSC(pin 15) input directly.
DIVIDE-BY-8
SCR
COUNTER
(0)RESET
1COUNT
45. M5 inSIGNAL SYSTEM SELECT input
See the description of the M6(pin 37) input.
BKPF-0125-5 |
ACEC
SONY
