DSR-7.3
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-5
Q8501: CS493292-CL (Multi-Standard Audio Decoder)
TERMINAL DESCRIPTION
AUDATA1---Digital Audio Output 1: Pin 40
PCM multi-format digital-audio data output, capable of two-channel 20-bit output.
This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT
AUDATA0---Digital Audio Output 0: Pin 41
PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bit output.
This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT
MCLK---Audio Master Clock: Pin 44
Bidirectional master audio clock. MCLK can be an output from the CS493XX that provides an
oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs.
MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when SCLK and LRCLK are driven
by the CS493XX. BIDIRECTIONAL - Default: INPUT
SCLK---Audio Output Bit Clock: Pin 43
Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLK
to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and the digital-output configuration.
SCLK can also be an input and must be at least 48Fs or greater.
As an input, SCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT
LRCLK---Audio Output Sample Rate Clock: Pin 42
Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that is divided from MCLK to provide the output sample rate
depending on the output configuration.
LRCLK can also be an input. As an input LRCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT
AUDATA3,XMT958---SPDIF Transmitter Output, Digital Audio Output 3: Pin 3
CMOS level output that contains a biphase-encoded clock for synchronously providing two
channels of PCM digital audio or a IEC61937 compressed-data interface or both.
This output typically connects to the input of an RS-422 transmitter or to the input of an optical transmitter.
Conversely this pin can be configured to be a third digital audio output. OUTPUT
SCLKN1, STCCLK2---PCM Audio Input Bit Clock: Pin 25
Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode.
In slave mode, SCLKN1 operates asynchronously from all other CS493XX clocks.
In master mode, SCLKN1 is derived from the CS493XX internal clock generator. In either master
or slave mode, the active edge of SCLKN1 can be programmed by the DSP.
For applications supporting PES layer synchronization this pin can be used as STCCLK2, which provides a path to the internal STC 33 bit counter.
BIDIRECTIONAL - Default: INPUT
LRCLKN1---PCM Audio Input Sample Rate Clock: Pin 26
Bidirectional digital-audio frame clock that is an output in master mode and an input in slave mode.
LRCLKN1 typically is run at the sampling frequency.
In slave mode, LRCLKN1 operates asynchronously from all other CS493XX clocks.
In master mode, LRCLKN1 is derived from the CS493XX internal clock generator.
In either master or slave mode, the polarity of LRCLKN1 for a particular subframe can be programmed by the DSP. BIDIRECTIONAL - Default: INPUT
SDATAN1---PCM Audio Data Input Number One: Pin 22
Digital-audio data input that can accept from one to six channels of compressed or PCM data.
SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has been configured. INPUT
CMPCLK, SCLKN2---PCM Audio Input Bit Clock: Pin 28
Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode.
In slave mode, SCLKN2 operates asynchronously from all other CS493XX clocks.
In master mode, SCLKN2 is derived from the CS493XX internal clock generator.
In either master or slave mode, the active edge of SCLKN2 can be programmed by the DSP.
If the CDI is configured for bursty delivery, CMPCLK is an input used to sample CMPDAT. BIDIRECTIONAL - Default: INPUT
CMPREQ, LRCLKN2---PCM Audio Input Sample Rate Clock: Pin 29
When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital audio frame clock that is an output
in master mode and an input in slave mode. LRCLKN2
typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronously
from all other CS493XX clocks. In master mode, LRCLKN2 is derived from the CS493XX internal clock generator.
In either master or slave mode, the polarity of LRCLKN2 for a particular subframe can be programmed by the DSP.
When the CDI is configured for bursty delivery, or parallel audio data delivery is being used, CMPREQ is an output which serves as an internal FIFO monitor.
CMPREQ is an active low signal that indicates when another block of data can be accepted. BIDIRECTIONAL - Default: INPUT
CMPDAT, SDATAN2---PCM Audio Data Input Number Two: Pin 27
Digital-audio data input that can accept from one to six channels of compressed or PCM data.
SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has been configured.
Similarly CMPDAT is the compressed data input pin when the CDI is configured for bursty delivery.
When in this mode, the CS493XX internal PLL is driven by the clock recovered from the incoming data stream. INPUT
DC---Reserved: Pin 38
This pin is reserved and should be pulled up with an external 4.7k resistor.
DD---Reserved: Pin 37
This pin is reserved and should be pulled up with an external 4.7k resistor. |
ACEC
ONKYO
