DTR-6.5
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS
IC42S16100 (16-Mbit Synchronous Dynamic RAM)
TERMINAL DESCRIPTION
Pin No.Pin name Function
20 to 24A0-A10A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input
27 to 32and A0-A7 as column address inputs during read or write command input. A10 is also used to
determine the precharge mode during other commands. If A10 is LOW during precharge command,
the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically after
the burst access.
These signals become part of the OP CODE during mode register set command input.
19A11A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is
selected. This signal becomes part of the OP CODE during mode register set command input.
16CASCAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth
Table" item for details on device commands.
34CKEThe CKE input determines whether the CLK input is enabled within the device.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode,
or the self refresh mode. The CKE is an asynchronous input.
35CLKCLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired
in synchronization with the rising edge of this pin.
18CSThe CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in
the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9,I/O0I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and
11, 12, 39, 40,to UDQM pins.
42, 43, 45, 46,I/O15
48, 49
14, 36LDQM,LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and
UDQMUDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to theHIGH
impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to
the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device.
17RASRAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth
Table" item for details on device commands.
15WEWE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth
Table" item for details on device commands.
7, 13, 38, 44CCQVVCCQ is the output buffer power supply.
1, 25CCVVCC is the device internal power supply.
4, 10, 41, 47GNDQGNDQ is the output buffer ground.
26, 50GNDGND is the device internal ground. |
ACEC
INTEGRA
