Interrupt and Exception Handler
An Interrupt and Exception Handler is responsible for managing all system and core exceptions.
There are four different kinds of exceptions that are executed in a similar way:
8 Interrupts generated by the Interrupt Controller (ITC)
8 DMA transfers issued by the Peripheral Event Controller (PEC).
8 Software traps caused by the TRAP instruction
8 Hardware traps issued by faults or specific system states
Normal Interrupt Processing
The CPU temporarily suspends the current program execution and branches to an Interrupt Service Routine (ISR) in order to
service an interrupt-requesting device. The current program status [Instruction Pointer (IP), Processor Status Word (PSW),
and in segmentation mode, the Code Segment Pointer (CSP)] is saved on the internal system stack.
A prioritization scheme with 16 priority levels and with 8 sub-levels (8 group levels) specifies the order of multiple
interrupt-request handling.
The maximum number of interrupt requests supported by the core architecture is 112 (configured in steps of 16).
Software and Hardware Traps
Trap functions are activated in response to special conditions that occur during the execution of instructions.
A trap can also be caused externally by the Non-Maskable Interrupt (NMI) pin. Several hardware trap functions are provided
for handling erroneous conditions and exceptions that arise during the program execution. Hardware traps always have
highest priority and cause immediate system reaction. The software trap function is invoked by the TRAP instruction, which
generates a software interrupt for a specified interrupt vector. For all types of traps, the current program status is saved in the
system stack.
Interrupt Processing via the Peripheral Event Controller
A faster alternative to normal interrupt processing is servicing an interrupt requesting device by the C166S's integrated PEC.
Triggered by an interrupt request, the PEC performs a single-word or byte data transfer between any two memory locations
through one of 16 programmable PEC service channels. During a PEC transfer, the normal program execution of the CPU is
halted. No internal program status information needs to be saved. The same prioritization scheme is used for PEC service as
for normal interrupt processing.
 General Purpose I/O
The MCU can configure the pin functionality of most of the pins after reset. Whether those pins show GPIO functionality or
one of the alternate functions ALT0 or ALT1 is defined by the PxCONF and PxALTSEL registers.
Because some of input functions appear on more than one pin, the PINSEL register must specify the respective pin. In case
of ASCx the active input needs to be set by the SxPISEL register of ASCx.
For peripherals which are not able to select or disable their input signal, the corresponding input signal must be enabled by
the INPEN register.
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