APPENDIX
IC DESCRIPTION
Pin 51 - Supply Voltage, Digital Circuitry VSUPD*Pin 65, 66 - Crystal Output / Input XTAL2 / XTAL1
These pins are connectecd to an 5-MHz crystal oscillator.
Pin 52 - Ground, Digital Circuitry GNDD*The security unit for the HOUT signal uses this clock sig-
Digital Circuitry Input Referencenal as reference.
2
Pin 53 - Main Clock Input LLC2(53)Pin 67 - Data Input/Output I CSDA
2
This is the input for the line-locked clock signal. The fre-Via this pin the - bus data are written to or read from I C
quency can be 27, 32, or 40.5 MHz.the DDP 3310B.
2
Pin 68 - Clock Input I CSCL
Pin 54...61 - Picture Bus Luma Y0...Y7
2
The Picture Bus Luma lines carry the digital luminance Via this pin, the clock signal for the -bus will be sup-I C
plied. The signal can be pulled down by an internal tran-
data.
sistor.
Pin 62 - Line-Locked Clock Input LLC1
* Application Note :
This is the reference clock for the single frequency input
All ground pins should be connected separeately with
sync signals required in a FIFO application. The frequency
short and low-resistive lines to a central power supply
can be 13.5, 16, or 20.25 MHz.
ground. Accordingly, all supply pins should be connected
separately with short and low-resistive lines to the power
Pin 63 - Sync Signal Input HS
supply. Decoupling capacitors from VSUPP to GNDP,
This pin gets the horizontal sync information. Either single
VSUPD to GNDD, and VSUPO to GNDO are recom-
or double horizontal frequency or VGA horizontal sync sig-
mended to be placed as closely as possible to the pins.
nal.
Pin 64 - Sync Signal Input VS
This pin gets the vertical sync informatoion. Either single
or double vertical frequency or VGA vertical sync signal.
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ACEC
