Section IV Models 78100A, 78101A
Principles of Operation
4-53. The input to the IF amplifier is parallel-tuned by output to a signal produced by a frequency-sensitive phase
L26, C44, and C45. C44 and C45 are tuned to step down shifting of the IF output. This phase shifting is done by
the input impedance to 385 ohms. The output collector is C66, L33, and Y2, which are connected in series. At the
parallel-tuned by L27 and C51. C52 provides dc isolation resonant frequency of crystal Y2, the IF output is phase
between the stages. C46 bypasses the bias diode and C50 shifted approximately +90° by C66 and L33.
assures that the base of the second stage of the IC is at ac
ground. 4-60. C71 is an averaging capacitor that establishes the
level of the descriminator output voltage. When the IF
4-54. The second IF integrated circuit is identical to the output and the phase-shifted signal are exactly 90" apart, as
first except that it is loaded by R26 to provide the proper shown in the solid waveforms in Figure: 4-3, the voltage on
source impedance to two-pole crystal filter FL2, which is C71 is in the middle of the output range. It is being charged
placed between U2 and U3 in order to eliminate noise half of the time and discharged the other half. When the
generated by U1 and U2. The bandwidths of the L-C tank two signals differ in phase by more than 90" (dashed
circuits are large enough that, without FL2, the IF waveforms), the voltage on C7 1 becomes lower, to indicate
amplifier noise would be the limiting factor in receiver a frequency decrease. C71 is charged through resistor R, in
sensitivity. U3 toward +12V, the charging current being proportional
to +12V minus the voltage on C71. C71 is discharged by a
circuit in U3 that consists of three differential pairs of
4-55. The IF amplifier portion of U3 consists of 3 transistors interconnected so that whenever the basic IF
differential stages joined by emitter followers. A third
output and the phase shifted IF output differ in algebraic
emitter follower is the output stage. Bias is achieved by dc
sign (Figure 4-3), one of the two transistor collectors
feedback from the output to the input differential stage. connected to C71 discharges C71. For phase shifts equal to
C6'4 and C65 assure that this path is broken for high
90°, as previously stated, current is withdrawn from C71
frequencies. L32 dc-connects the other base of the input
half of the time. If a decrease in frequency causes Y2 to
differential stage to the diode string. Differential stages are increase the phase shift, current is withdrawn from C71
used to assure that they can be driven into limiting without
more than half of the time. This causes the voltage on C71
transistor saturation (the limiting condition is cut-off of
to decrease, until the current through RL increases enough
first one transistor and then the other). R30 lowers the to keep the average current into C71 equal to zero. The
input impedance of U3 so the proper load impedance is average current is zero since the average charging current
presented to FL2. C63 provides dc decoupling and L32
through RL equals the average discharging current through
tunes out the input capacitance as well as other stray the differential transistor circuit. The output of the
capacitance on the board. The output from the output discriminator is buffered from C71 by an emitter follower
emitter follower (pin 10) is limited to two diode drops peak
in U3. Network R32, C20, and L36 filters the output, and
to peak. An attenuated (20 db) output is on pin 9. R32 prevents damage to the discriminator if its output is
shorted to ground or to either supply.
4-56. AGC Amplifier.
4-61. Low Frequency Board.
457. If Q7 conducts, increased current flows in R20 of the
mixer circuit. This increases the source to gate back bias of
4-62. The low frequency board 78101-60740 (schematic,
Q6, reducing its bias current, and hence the mixer gain. By Figure 6-7) processes the subcarrier signal to reproduce the
this feedback mechanism the signal amplitude at TPl is ECG signal, evaluates the subcarrier, and detects inoperative
limited, to prevent UI or U2 from saturating. For low
conditions based on its amplitude and frequency. The
signals on TPl, Q7 is biased off by R27. However, if the ac power supply and automatic frequency control amplifier
voltage coupled through C61 exceeds 2 diode drops peak to are also contained on the low frequency board.
peak, Q7 will conduct at the maximum point of the signal.
The conducted current pulses are smoothed by C62. The dc 4-63. Buffer Amplifier.
voltage on the emitter of Q7 increases, raising the voltage
on the source of Q6, through R28, L25, and L23. R28 and
464. Emitter follower Q4 prevents excessive loading of the
C47 filter low frequencies and prevent frequency instability discriminator. R14 is its load resistor and R13 prevents high
of the loop. frequency oscillation due to the inductance of the wire
from feed-through capacitor C30. 1
4-58. FM Discriminator Circuit.
465. Subcarrier Filter.
4-59. The quadrature discriminator produces a voltage that
is proportional to frequency. It works by comparing the IF 4-66. U6 is connected as a three pole low pass active filter.
46 078 100-2 |
ACEC
