Chrominance Circuitry
Chrominance input S3 is via SVHS socket J303, E302/E301 pin 7 and C354, R522 to pin 16 of I201.
When operating input S3 via SVHS socket J303, the mP, I001 pin 15 is "h igh" turning on Q005 and
pulling down pin 16 of I201 to around 4V from SV, this removes the luminance notch and allows pin
16 of I201 to be a chroma input.
When receiving PAL, I201 performs demodulation of the signal input to pin 15, and the R -y and B -y
colour signals are output from I201 at pins 30 and 31. They are then fed to pins 14 and 16 of I501
which is a switch capacitor delay line.
The inputs at pins 14 and 16 are clamped, then fed via a buffer stage to internal delay lines, which are
driven by a c lock signal of 3 MHz, to obtain a delay period of 64p,S. This internal clock is generated
from a 6 MHz voltage controlled oscillator, and line locked by the sandcastle pulse input at pin 5. Low
pass filters after the delay line stages suppress the unwanted clock signals.
The undelayed and delayed signals are then added, with the resulting R -y and B-y signals being output
from pins 11 and 12 via an internal buffer stage. These outputs are then returned to I201 at pins 28 and
29.
The IC contains clamping ci rcuits and a DC colour saturation control, the level of which is set by the
voltage applied to pin 26 from pin 4 of I001. The signals are then applied to a MATRIX circuit, and
finally emerges from pins 18, 19 and 20 as the blue, green and red signals.
When receiving NTSC signals, pin 27 is between 0 -5V operating as the hue contro1 originating from
pin 3 of I001 via R063, R078, R116 and L052.
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ACEC
