Table 3-5-10 (1/5) TMP94CS40AFTable 3-5-10 (2/5) TMP94CS40AF
PinPin
No.NameFunctionNo.NameFunction
77 P00 - P07Port 0: I/O port.70P75Port 75: I/O port.
|D0 - D7Data 0-7: data bus 0-7.BUSRQBus request: signal with memory interface
84Function is selectable by setting of AM0/1terminal requested to be high impedance.
terminal.The following pins become high
It becomes high impedance at no externalimpedance, but no change is made when
memory access.used as a port.
A0 - A23, D0 - D31, RD, WRLL, WRLH,
86P10 - P17Port 1: I/O port.
WRHL, WRHH, CS0 - CS5, OE0 - OE1,
|D8 - D15Data 8-15: data bus 8-15.
WE0-WE1, RAS group, CAS group
93Function is selectable by setting of AM0/1
terminal.69P76Port 75: output port. (Initializes to ?1? output.)
It becomes high impedance at no externalBUSAKBus acknowledge: signal, that indicates
memory access.request of BUSRQ received.
95 P20 - P27Port 2: I/O port.67P80Port 80: output port. (Initializes to ?1? output.)
|D16 - D23Data 16-23: data bus 16-23.CS0Chip select 0: ?L? level is developed if
102Function is selectable by setting of AM0/1address is within the assigned address
terminal.range.
It becomes high impedance at no external
66P81Port 81: output port. (Initializes to ?1? output.)
memory access.
CS1Chip select 1: ?L? level is developed if
104 P30 - P37Port 3: I/O port.address is within the assigned address
|D24 - D31Data 24-31: data bus 24-31.range.
111Function is selectable by setting of AM0/1RAS0Low address strobe 0: RAS strobe signal
terminal.for DRAM is developed if address is within
It becomes high impedance at no externalthe assigned address range.
memory access.
65P82Port 82: output port. (Initializes to ?0? output.)
113 P40 - P47Port 4: I/O port.CS2Chip select 2: ?L? level is developed if
|A0 - A7Address 0-7: address bus 0-7.address is within the assigned address
120Function is selectable by setting of AM0/1range.
terminal.
64P83Port 83: output port. (Initializes to ?1? output.)
Signal does not change at no external
CS3Chip select 3: ?L? level is developed if
memory access.
address is within the assigned address
122 P50 - P57Port 5: I/O port.range.
|A8 - A15Address 8-15: address bus 8-15.RAS1Low address strobe 1: RAS strobe signal
129Function is selectable by setting of AM0/1for DRAM is developed if address is within
terminal.the assigned address range.
Signal does not change at no external
63P84Port 84: output port. (Initializes to ?1? output.)
memory access.
CS4Chip select 4: ?L? level is developed if
131 P60 - P67Port 6: I/O port.address is within the assigned address
|A16 - A23Address 16-23: address bus 16-23.range.
138Function is selectable by setting of AM0/1
62P85Port 85: output port. (Initializes to ?1? output.)
terminal.
CS5Chip select 5: ?L? level is developed if
Signal does not change at no external
address is within the assigned address
memory access.
range.
75P70Port 70: output port. (Initializes to ?1? output.)
49P86Port 86: I/O port.
RDRead: strobe signal reading external memory.
WAITWait: Bus wait request signal
Function is selectable by setting of AM0/1
terminal.60PA0Port A0: output port. (Initializes to ?1? output.)
Strobe signal is not developed at noCAS0Column address strobe 0: CAS strobe
external memory access.signal for DRAM is developed if address is
within the assigned address range.
74P71Port 71: output port. (Initializes to ?1? output.)
LCAS0Lower column address strobe 0: lower CAS
WRLLWrite: strobe signal writing D0-D7 of
strobe signal for DRAM is developed if
external memory.
address is within the assigned address
Strobe signal is not developed at no
range.
external memory access.
59PA1Port A1: output port. (Initializes to ?1? output.)
73P72Port 72: output port. (Initializes to ?1? output.)
UCAS0Upper column address strobe 0: upper CAS
WRLHWrite: strobe signal writing D8-D15 of
strobe signal for DRAM is developed if
external memory.
address is within the assigned address
Strobe signal is not developed at no
range.
external memory access.
58PA2Port A2: output port. (Initializes to ?1? output.)
72P73Port 73: output port. (Initializes to ?1? output.)
OE0Out enable 0: out enable signal for DRAM is
WRHLWrite: strobe signal writing D16-D23 of
developed.external memory.
Strobe signal is not developed at no57PA3Port A3: output port. (Initializes to ?1? output.)
external memory access.OE1Out enable 1: out enable signal for DRAM is
developed.
71P74Port 74: output port. (Initializes to ?1? output.)
WRHHWrite: strobe signal writing D24-D31 of56PA4Port A4: output port. (Initializes to ?1? output.)
external memory.WE0Write enable 0: write enable signal for
Strobe signal is not developed at noDRAM is developed.
external memory access.
3-33 |
ACEC
