GB 1029.EM3ECircuit Descriptions and Abbreviation List
The sandcastle pulse from the HOP is fed to pin 1 of theEast/West Drive
TOPIC, which is used as reference for timing.At pin 3, the E/W-drive is available. Pin 4 is a feedback input
for the EHT-info, and is used to prevent pumping of the
9.8.2 Video Controlpicture. The EHT varies also dependent on the beam current.
For wide-screen without load this is 31.5 kV and with load
(1.5 mA) 29.5 kV.
After source selection, the HOP controls the signals for
Saturation, Contrast and Brightness. Output is RGB again.
Frame Rotation
For frame rotation, a control voltage is used from pin 25 of the
9.8.3 OSD/TXT Control
HOP. Frame rotation is only used in wide-screen sets.
On pins 35 to 38 the RGB and fast blanking from the OTC
9.8.8 Protections
(OSD and TXT) are inserted. The sync signal VSYNC)is
derived from the ?FRAMEDRIVE-? signal.
Flash detection
When a flash occurs, the EHT-info will become negative very
9.8.4 Peak White Limiting
fast. Via R3316/D6304/D6303, TS7303 starts to conduct.
This makes pin 5 of HOP ?high?. The output (pin 8) is
On pin 43 there is a Peak White Limiting signal line (PWL). If
immediately stopped.
the beam current increases, the ?EHT-info? voltage will
If the H-drive stops, then also pin 5 will become ?low? again,
decrease. Average limiting via R3343/C2333 controls PWL.
which will reset the flash detection.
A bit (FLS) is set in an output status register, so that the OTC
9.8.5 Cut-off Controlcan see that there was a flash. This FLS-bit will be reset
when the OTC has read that register.
The following will happen when you switch the TV to
Standby:HFB protection
1. The vertical scan is completed.If the HFB is not present, it this detected via the HOP. The
2. The vertical flyback is completed (the horizontal output isOTC puts the TV into protection and reads a register in the
gated with the flyback pulse, so that the horizontal outputHOP. An error code is generated.
transistor cannot be switched ?on? during the flyback
pulse).
3. The ?slow stop? of the horizontal output is started, by9.9Synchronisation (diagram B2, B3 & B4)
gradually reducing the 'on' time at the horizontal output
from nominal to zero (this will take 50 ms).The HIP video processor provide the vertical and horizontal
4. At the same time, the fixed beam current is forced via thesync pulses VA and HA. They are synchronised with the
black-current-loop for 25 ms. This is done by setting theincoming CVBS signal. Then these pulses are fed to the
RGB outputs to a maximum voltage of 5.6V.PICNIC, where they are doubled to be synchronous with the
100 Hz picture. The outgoing pulses, VD100 and HD100,are
In the EM3E a 'one-point' cut-off control is used:fed to the HOP, which supplies the vertical and horizontal
A current of 8A (for cut-off) is fed to pin 44 of the HOP. Thisdrive pulses and the 100 Hz (2fH) sandcastle pulse.
is done with a measurement pulse during the frame flyback.
During the 1st frame, 3 pulses are generated to adjust theThe VD100 pulse from the PICNIC is inverted by TS7304 to
cut-off voltage at a current of 8A. With this measurementthe VD signal. The OTC is synchronised on the HFB pulse
the black level at the RGB-outputs is adjusted.from the CRT and on the VSYNC from the HOP, for the
So at start-up there is no monitor pulse anymore. At start-up,synchronisation of TXT/OSD/EPG
the HOP measures the pulses, which come back via pin 44.
The RGB-outputs have to be between 1.5 V and 3.5 V. If oneWhen no CVBS is offered to the video processor, the VA50
of the outputs is higher than 3.5 V or one of them lower thenand HA50 pulses are switched ?off? by the HIP, and the pulses
1.5 V, the RGB-outputs will be blanked.are generated by the PICNIC (to assure a stable OSD).
9.8.6 Geometry control
All geometry control is done via I2C and the data is stored in
the NVM (IC7011) of the SSB.
9.8.7 Deflection Control
Line Drive
The Line drive is derived from an internal VCO of 13.75 MHz.
As a reference, an external resonator is used (1301). The
internal VCO is locked with the HD100-pulse, which comes
from the PICNIC.
The 'PHI-2' part in the HOP receives the HFB_X-RAY_PROT
(pin 13) to correct the phase of the Line drive. The EHT-info
is supplied to pin 14 (DYN-PHASE-CORR) to compensate
picture breathing depending on the beam current.
Note: This is not used in the EM3E, therefore EHT-
compensation in the SAM menu is put to zero.
Frame Drive
At pins 1 and 2 the symmetrical frame drive signals are
available. The VSYNC signal, for synchronisation of the OSD/
TXT, is derived from the ?FRAMEDRIVE-? signal. |
ACEC
