Circuit Descriptions, List of Abbreviations, and IC Data Sheets FM23, FM24, FM339.EN 137
Sync PathIt also is a "must" when a computer graphics card is connected,
All incoming H and V sync signals go to a 4-pole switch (item because there is no, or very little, post anti-aliasing filtering
7009) where SYNC_SEL and VIDEO_SEL_2 determine, which done on such cards. Therefore, the outputted RGB samples
signal is available on the ADC.need to be exactly aligned with the sampling of the AD
Before this switch, the VGA sync path is rather straight, only 1 converter.
switch (item 7007) is added for the VGA2 sync signals, which Analogue input signals can go up to "SXGA at 75 Hz" format,
determines if VGA2 sync is input or output (VGA2_OUT).which gives a pixel clock of 135 MHz. In fact, it can handle any
In the Basic configuration, these switches are omitted, and standard with a pixel rate up to 140 MHz.
replaced by jumpers (4009/4010).Special modes are made for the F21R E-box, for both PAL and
NTSC. These are invoked when an E-box is connected to the
The external sync (AV1 - 3) signals are treated differently. Both SCAVIO panel.
H_HD_EXT and V_HD_EXT go to three circuits:
A comparator circuitry with an LM319 (item 7025), to Digital input: Via the DVI connector (Enhanced version only)
ensure both sync pulses are always positive going (H and it is possible to insert TMDS (Transition Minimised Differential
V_SYNC_CMP),Signalling) data into the SCAVIO panel. DVI is a fairly new
A level detection circuitry (items 7000 to 7002), to detect if computer graphics standard, which can be seen as the digital
the sync is of TTL level (H and V_SYNC_TTL),follow-up of the analogue VGA interface. The TMDS signal is
A positive/negative going detection circuitry (items 7006 to directly fed into the AD9887, where any DVI standard up to
7010), to indicate the polarity of the sync in case of TTL "SXGA at 60 Hz" can be decoded to RGBHV.
level (H and V_SYNC_POL_N).The preferred VGA standard for this chassis is programmed in
All above-mentioned signals go to the EPLD (see diagram the DDC EEPROM (item 7215), which can be read by the PC.
SC11) for further processing.Via an internal switch, it is possible to choose between the
analogue input and the digital input. The output format is for
Processed sync signals H_HD and V_HD coming from the both inputs the same (8 bit RGB plus HV). The driver
EPLD, are also switched to the ADC (H_ADC and V_ADC) determines whether the AD9887 outputs single or dual pixels.
along with the proper RGB signals (R_ADC, G_ADC and For lower standards like "VGA at 60 Hz", the interface will be
B_ADC).single pixel, which means that every clock cycle one byte of R,
G, and B data is outputted. Dual pixel means that on every
Digital Videoclock cycle two bytes of R, G, and B data outputted. These two
This part describes the digital video path on the SCAVIO panel, bytes are de-multiplexed, which is done to make the interface
starting at the AD converters in either the AD9887 (item 7170) more robust for jitter, set-up, and hold times, and to reduce the
or in the SAA7118E (item 7225) and ending at the output for the digital data rate over the PCB (reduced EMC).
PDP.
For both the Basic as the Enhanced version, everything "after" Digital "Video Path"
the Pixel Works chip, is equal. This path is only available in the Enhanced version of the
For the Basic version, the input for the Pixel Works only SCAVIO panel and is used for the following input signals:
consists of the "Graphics path". CVBS input,
For the Enhanced version, it is both the "Graphics path" as the Y/C input, and
"Video path".1fH YPbPr.
The SCAVIO panel contains the following functions in the video It is a straightforward application of the Philips SAA7118 (item
path:7225) and the Micronas SDA9400 (item 7280).
1. The "YPbPr to RGB matrix" and "2fH Video+Sync Switch" The SAA7118 is a PAL/NTSC/SECAM Digital Video Decoder
are explained above in the "Analogue Video" part.with adaptive digital comb filter and component video input. It
2. The "Digital Video" path containing the Digital Video decodes all input standards to 4:2:2 YCbCr, which then is
Decoder and the De-interlacer.processed by the SDA9400.
3. The "Digital Graphics" path containing the ADC+TMDS
decoder.The SDA9400 is a motion adaptive de-interlacer, which makes
4. The "Scaler" which is the Pixel Works (PW164-10R) plus a progressive video signal from the interlaced input.
Memory.Depending on the motion in the picture, it will just interleave the
5. The "EPLD" for sync decoding and video manipulation.odd and even field (no motion: ABAB) or repeats the same field
6. The "LVDS" encoder.twice; this is also known as line doubling (motion: AABB). The
motion detection is pixel based, with a soft-switch between
The Digital "Graphics Path""motion" and "no motion".
This is a straightforward application of the Analogue Devices
AD9887 (item 7170). Inputs for this device are: After the de-interlacer, the signal is fed as a 4:2:2 YCbCr
FTV Receiver box,progressive scan signal to the video port of the Pixel Works
VGA formats (up to SXGA at 75 Hz),processor.
2fH RGB+HV (only in Enhanced version),
2fH YPbPr, which is converted to RGB by the "YUV to The Pixel Works PW164 Scaler
RGB" matrix (only in Enhanced version),The Pixel Works PW164 Image Processor is a highly
DVI-d (only in Enhanced version).integrated (Ball Grid Array, BGA) chip, which interfaces video
inputs and computer graphics in virtually any format to the
Analogue input: The AD9887 is meant to sample "pixel PDP.
synchronous". To achieve this, a (software) driver is running on
the Pixel Works processor (PW). After hooking up a source to Computer images from VGA to UXGA resolution input to the
the AD9887, the PW starts counting the number of lines per chip can be resized to fit on the PDP. Horizontal and vertical
field and calculates the H-period time. With these two values, it image scalers, coupled with intelligent frame locking circuitry
determines the exact match or the closest match out of a look-create sharp images, centred on the screen and without user
up-table (LUT) with VGA standards. When the correct standard intervention. An embedded DRAM frame buffer and memory
is determined, the PW will set the AD9887 I2C registers to the controller perform the frame rate conversion.
correct value. The AD9887 should now sample with exact the
same frequency as the incoming standard requires. This is Video data from 4:3 aspect ratio NTSC or PAL and 16:9 aspect
done to get an optimal picture performance. ratio sources such as HDTV and DVD are supported. Non- |
ACEC
