IC BLOCK DIAGRAM & DESCRIPTION
IC820 ZR36732 (MPEG)
Status After RESET/Status After RESET/
PinNameTypeDirectionDuring STANDBYPinNameTypeDirectionDuring STANDBY
SDRAM Interface (35 pins).Test Signal Interface (3 pins).
90RAMDAT[15]3-SI/O (r.t.)Reset: input (p.d.)125SCNENBLIIInput
87RAMDAT[14]Standby: 3-S (p.d.)Production test pin (connected directly to GNDP in normal operation).
84RAMDAT[13]129TESTMODEIIInput
81RAMDAT[12]In normal operation this pin must be connected directly to GNDP.
78RAMDAT[11]112ICEMODE#IIInput
75RAMDAT[10]In normal operation this pin must be connected directly to VDDP. If it is asserted, then the ADP goes into ICE mode. In
72RAMDAT[9]this mode 4 of the Decoder pins turn into ICE interface pins:
68RAMDAT[8]HD[11] = TCK ? ICE interface clock
70RAMDAT[7]HD[10] =TMS ? ICE interface mode select input
74RAMDAT[6]HD[9] = TDO ? ICE interface data output
76RAMDAT[5]HD[8] = TDI ? ICE interface data input
79RAMDAT[4]
82RAMDAT[3]Power Signals (49 pins).
85RAMDAT[2]
88RAMDAT[1]*GNDP(* pins 10, 40, 49, 56, 65, 69, 80, 86, 97,
91RAMDAT[0]128, 146)
SDRAM bidirectional data bus.Digital ground of 3.3 V supply.
55RAMADD[11]OO (p.d.)Reset: output*V(* pins 3, 16, 19, 26, 38, 44, 52, 58, 67, 71,
53RAMADD[10]Standby: 3-SDDP77, 83, 89, 94, 98, 99, 126, 135, 140)
54RAMADD[9]3.3 V Digital power supply.
51RAMADD[8]
48RAMADD[7]132GNDP-A2
46RAMADD[6]Digital ground of filtered 3.3 V supply for AMCLK.
43RAMADD[5]130VDDP-A2
41RAMADD[4]3.3 V filtered digital power supply for AMCLK.
42RAMADD[3]*GNDC(* pins 14, 35, 73, 114, 144)
45RAMADD[2]Digital ground of 1.8 V supply.
47RAMADD[1]*VDDC(* pins 12, 33, 63, 116, 142)
50RAMADD[0]1.8 V Digital power supply.
SDRAM address bus output.123GNDA
60RAMRAS#OO (p.u.)Reset: outputGround plane of internal PLL circuit.
Standby: 3-S (p.u.)121VDDA
SDRAM row select output.1.8 V Power supply for internal PLL circuit.
61RAMCAS#OO (p.u.)Reset: output104VDDDAC
Standby: 3-S (p.u.)3.3 V Analog power supply for the DACs.
SDRAM column select output.101GNDDAC_D
66PCLKOO (p.d.)Reset: output107GNDDAC_B
Standby: 3-S109GNDDAC_P
SDRAM clock output (Same as internal processing clock).110GNDDAC_S
64RAMDQMOO (p.d.)Reset: outputGrounds for the DACs 3.3 V analog power supply
Standby: 3-S (p.u.)
SDRAM data masking output.
57RAMCS0#OO (p.u.)Reset: outputIC821 K4S16162D
Standby: 3-S (p.u.)
SDRAM chip select output for the lower (or only) 2MB device (16Mbit).(512 X 16Bit X 2 Bank synchronous DRAM )
59RAMCS1#OO (p.u.)Reset: output
Standby: 3-S (p.u.)
SDRAM chip select output for the upper 2MB device (16Mbit).
62RAMWE#OO (p.u.)Reset: output
Standby: 3-S (p.u.)
SDRAM write enable output.LWE
Data Input Register
I/O Control14LDQM
IC870 PCM1602Y (Digital to Analog Controller)Bank Select
BCK 40DACOutput Amp and14 VOUT1512K x 162,3,5,6,7,8,9,11,
LRCK 41Low-pass Filter12,39,40,42,43,DQ1
DATA1(1,2) 45InputOutput Amp and13 VOUT2CLK 35512K x 16Sense AMPSerial45,46,48,49
DACRow BufferRow DecoderOutput Buffer
DATA2(3,4) 46I/FLow-pass FilterRefresh Counter
DATA3(5,6) 474x / 8xADD 20~24,27~32
OversamplingEnhancedDACOutput Amp andLow-pass Filter12 VOUT3Column Decoder
Multi-levelDigital FilterAddress Register
withDelta-Sigma
FunctionModulatorDACOutput Amp and15 VCOMLRASLCBRLatency & Borst Length
TEST 42ControllerLow-pass Filter11 VOUT4
RST 37Col. Buffer
ML 36FunctionDACOutput Amp and10 VOUT5LCKEProgramming Register
Low-pass Filter
MC 35ControlLRASLCBRLWELDQM
I/FLCASLWCBR
MDI 34
MDO 33DACLow-pass FilterOutput Amp and9 VOUT6
Timing Register
System Clock
35341817161536
SCKI 38System ClockPower SupplyManagerZero Detect
CLKCKECSRASCASWEL(U)DQM
3948123456434428,26.2422,18 27,25.2321,17,19
VDD1-5 Pin NAME Input Function
ZEROAVCLKSystem ClockActive on the positive going edge to sample all inputs.SCKODGNDCC
AGND1-6
PIN ASSIGNMENTSCSChip SelectZERO1/GPO1ZERO2/GPO2ZERO3/GPO3ZERO4/GPO4ZERO5/GPO5ZERO6/GPO6Disables or enables device operation by masking or enabling all inputs except
CLK,CKE and L(U)DQM
PINNAMEI/ODESCRIPTION
1ZERO1/GPO1OZero Data Flag for VOUT1. Can also be used as GPO pin. Masks system clock to freeze operation from the next clock cycle.
2ZERO2/PGO2OZero Data Flag for VOUT2. Can also be used as GPO pin.CKEClock EnableCKE should be enabled at least one cycle prior to new command.
3ZERO3/PGO3OZero Data Flag for VOUT3. Can also be used as GPO pin.Disable input buffers for power down in standby.
4ZERO4/PGO4OZero Data Flag for VOUT4. Can also be used as GPO pin.
5ZERO5/PGO5OZero Data Flag for VOUT5. Can also be used as GPO pin.
6ZERO6/PGO6OZero Data Flag for VOUT6. Can also be used as GPO pin.A0 - A10/APAddressRow/column addresses are multiplexed on the same pins.
Row address : RA0 - RA10, Column address : CA0 - CA7
7NC-No Connection
8NC-No Connection
9VOUT6OVoltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz.BABank Select AddressSelects bank to be activated during row address latch time.
10VOUT5OVoltage Output of Audio Signal Corresponding to Lch on DATA3. Up to 96kHz.Selects bank for read/write during column address latch time.
11VOUT4OVoltage Output of Audio Signal Corresponding to Rch on DAYA2. Up to 96kHz.
12VOUT3OVoltage Output of Audio Signal Corresponding to Lch on DATA2. Up to 96kHz.Row Address StrobeLatches row addresses on the positive going edge of the CLK with RAS low.
13VOUT2OVoltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz.RASEnables row access & precharge.
14VOUT1OVoltage Output of Audio Signal Corresponding to Lch on DATA1. Up to 192kHz.
15VCOMOCommon Voltage Output. This pin should be bypassed with a 10uF capacitor to AGND.
16NCONo ConnectionCASColumn Address StrobeLatchea column addresses on the positive going edge of the CLK with CAS low.Enables column access.
17AGND5-Analog Ground
18VCC5-Analog Power Supply, +5V
19AGND6-Analog GroundWEWrite EnableEnables write operation and row precharge.
Latches data in starting from CAS, WE active.
20NC-No Connection
21AGND4-Analog Ground
22VCC4-Analog Power Supply, +5VL(U)DQMData Input/Output MaskMskes data output Hi-Z, ISHZ sfter the clock and masks the output.
23AGND3-Analog GroundBlocks data input when L(U)DQM active.
24VCC3-Analog Power Supply, +5V
25AGND2-Analog GroundDQ0 - 15Data Input/OutputData inputs/outputs are multiplexed on the same pins.
26VCC2-Analog Power Supply, +5V
27AGND1-Analog GroundVDD/VSSPower Supply/GroundPower and ground for the input buffers and the core logic.
28VCC1-Analog Power Supply, +5V
29NC-No ConnectionIsolated power supply and ground for the output buffers to provide improved noise
30NC-No ConnectionVDDQ/VSSQ Dsta Output Power/Groundimmunity.
31NC-No Connection
32NC-No Connection
33MDOOSerial Data Output for Function Register Control Port(3)N.C/RFUNo Connection/This pin is recommended to be left No Connection on the device.
34MDIISerial Data Input for Function Register Control Port(1)Reserved for Furure Use
35MCIShift Clock for Function Register Control Port(1)
36MLILatch Enable for Function Register Control Port(1)
37RSTISystem Reset, Active LOW(1)
38SCKIISystem Clock In. Input frequency is 128,192,256,384,512, or 768fs.(2)
39SCKOOBuffered Clock Output. Output frequency is 128,192,256,384,512, or 768fs or one-half of 128,192,256,384,512 or 768fs.
40BCKIShift Clock Input for Serial Audio Data.(2)
41LRCKILeft and Right Clock Input. This clock is equal to the sampling rate, fs.(2)
42TEST-Test Pin. This pin should be connected to DGND.(1)
43VDD-Digital Power Supply, +3.3V
44DGND-Digital Ground for +3.3V
45DATA1ISerial Audio Data Input for VOUT1 and VOUT2(2)
46DATA2ISerial Audio Data Input for VOUT3 and VOUT4(2)
47DATA3ISerial Audio Data Input for VOUT5 and VOUT6(2)
48ZEROAOZero Data Flag. Logical "AND" of ZERO1 through ZERO6.
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger inout, 5V tolerant. (3) Tri-state output.
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ACEC
