IC, LC74781M
Pin No.Pin NameI/ODescription
1VSS1NGND connection terminal. (Digital ground terminal).
2Xtal INIExternal XOtal and capacitor for internal sync generator, or the external clock are
3Xtal OUTOconnected to this terminal. (2fsc or 4fsc).
Either the external clock input mode or the XOtal generator mode is selected by this
4CTRL1I
selector terminal. L: XOtal generator mode, H: External clock input.
Blank signal (character and the green ORed signal) is output from this terminal.
________
5BLANKO(MODE 0: composite sync signal is output at H.) When reset (RST terminal = L), the
XOtal clock signal is output. (It is not output when reset by the reset command).
6OSC INIExternal coil and capacitor for the character output dot clock generator are connected
7OSC OUTOto this terminal.
The character signal is output from this terminal. (MOD 0: when H, the external sync
signal identification signal is output from this terminal. This output signal tells whether
8CHARAOthe external sync signal is present or not. When external sync signal is present, H is
________
output.) When reset (RST terminal = L), the dot clock signal (LC oscillator) is output.
(It is not output when reset by the reset command).
______Enable signal for the serial data input is input to this terminal. The serial data input is
9CSI
enabled at L. Pull-up resistor is built-in. (Hysteresis input).
Clock of the serial data input is input to this terminal. Pull-up resistor is built-in.
10SCLKI
(Hysteresis input).
11SINISerial data input terminal. Pull-up resistor is built-in. (Hysteresis input).
12VDD2NPower supply for the composite video signal level adjustment. (Analog power supply).
13CV OUTOComposite video signal output terminal.
14NCNConnected to GND or not connected.
15CV INIComposite video signal input terminal.
16VDD1NPower supply (+5V digital power supply).
Video signal for the internal sync separator circuit is input to this terminal. (When the
17SYN INIinternal sync separator circuit is not used, the horizontal sync signal or composite sync
signal is input to this terminal).
18SEP CNInternal sync separator circuit bias voltage monitoring terminal.
The composite sync output signal of the internal sync separator circuit is output from
Othis terminal. (H: MOD 1. H: during internal sync mode. L: during external sync
19SEP OUT
mode.) (When internal sync separator circuit is not used, the SYN IN input signal is
output from this terminal).
The output signal of the SEP OUT terminal is integrated so that the vertical sync signal
is input to this terminal. An integrator circuit must be connected between the SEP
20SEP INI
OUT terminal and this terminal. When this terminal is not used, it must be connected
to VDD1.
When selecting any of the NTSC or PAL or PAL-M or PAL-N system, the pin setting
has priority. When L, the NTSC system is selected after resetting. Selection of either
21CTRL2I
NTSC or PAL or PAL-M or PAL-N system by the command becomes effective. H:
PAL-M system.
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ACEC
AIWA
