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5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(6)
Power Management Interface Signals (Continued) Processor Interface Signals (Continued)
Signal Name Type Description Signal Name Type Description
DPRSLPVR O Deeper Sleep - Voltage Regulator: This signal is used to lower the IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error
voltage of VRM during C4 and S1-M states. When the signal is pin on the processor. IGNNE# is only used if the ICH4 coprocessor
high, the voltage regulator outputs the lower ?Deeper Sleep? error reporting function is enabled in the General Control Register
voltage. When the signal is low (default), the voltage regulator (Device 31:Function 0, Offset D0, bit 13). If FERR# is active,
outputs the higher ?Normal? voltage. During PCIRST#, the output indicating a coprocessor error, a write to the Coprocessor Error
driver is disabled and an internal pull-down is enabled. This is Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains
needed for implementing a strap on the pin. When PCIRST# asserted until FERR# is negated. If FERR# is not asserted when the
deasserts, the output driver is enabled. To guarantee no glitches on Coprocessor Error Register is written, the IGNNE# signal is not
the DPRSLPVR pin, the pull-down is disabled after the output asserted.
driver is fully enabled. Speed Strap: During the reset sequence, ICH4 drives IGNNE# high
NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a if the corresponding bit is set in the FREQ_STRP register.
functional strap. INIT# O Initialization: INIT# is asserted by the ICH4 for 16 PCI clocks to
reset the processor. ICH4 can be configured to support CPU BIST.
In that case, INIT# will be active when PCIRST# is active.
NMI O Non-Maskable Interrupt: NMI is used to force a non-Maskable
Processor Interface Signals interrupt to the processor. The ICH4 can generate an NMI when
Signal Name Type Description either SERR# or IOCHK# is asserted. The processor detects an NMI
when it detects a rising edge on NMI.
A20M# O Mask A20: A20M# will go active based on either setting the
appropriate bit in the Port 92h register, or based on the A20GATE NMI is reset by setting the corresponding NMI source
enable/disable bit in the NMI Status and Control Register.
input being active. Speed Strap: During the reset sequence, ICH4 drives NMI high if
Speed Strap: During the reset sequence, ICH4 drives A20M# high
if the corresponding bit is set in the FREQ_STRP register. the corresponding bit is set in the FREQ_STRP register.
SMI# O System Management Interrupt: SMI# is an active low output
CPUSLP# O CPU Sleep: This signal puts the processor into a state that saves synchronous to PCICLK. It is asserted by the ICH4 in response to
substantial power compared to Stop-Grant state. However, during
one of many enabled hardware or software events.
that time, no snoops occur. The ICH4 can optionally assert the STPCLK# O Stop Clock Request: STPCLK# is an active low output
CPUSLP# signal when going to the S1-M state.
FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor synchronous to PCICLK. It is asserted by the ICH4 in response to
one of many hardware or software events. When the processor
error signal on the processor. FERR# is only used if the ICH4 samples STPCLK# asserted, it responds by stopping its internal
coprocessor error reporting function is enabled in the General
clock.
Control Register (Device 31:Function 0, Offset D0, bit 13). If RCIN# I Keyboard Controller Reset CPU: The keyboard controller can
FERR# is asserted, the ICH4 generates an internal IRQ13 to its
interrupt controller unit. It is also used to gate the IGNNE# signal to generate INIT# to the processor. This saves the external OR gate
with the ICH4?s other sources of INIT#. When the ICH4 detects the
ensure that IGNNE# is not asserted to the processor unless FERR# assertion of this signal, INIT# is generated for 16 PCI clocks.
is active. FERR# requires an external weak pull-up to ensure a high
level when the coprocessor error function is disabled. NOTE: The ICH4 ignores RCIN# assertion during transitions to the
S1-M, S3, S4 and S5 states.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is A20GATE I A20 Gate: A20GATE is from the keyboard controller. The signal
acts as an alternative method to force the A20M# signal active. It
independent of the General Control Register bit setting. saves the external OR gate needed with various other PCIsets.
INTR O CPU Interrupt: INTR is asserted by the ICH4 to signal the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
Speed Strap: During the reset sequence, ICH4 drives INTR high if
the corresponding bit is set in the FREQ_STRP register.
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