61206120N N/B MAINTENANCEN N/B MAINTENANCE
3.33.3 INTEL 82371EB PCIINTEL 82371EB PCI--TOTO--ISA / IDE ISA / IDE XXCCELERATOR (PIIXELERATOR (PIIX4) (4).4) (4).
SIGNAL TYPE DESCRIPTIONSIGNAL TYPE DESCRIPTION
LA[23:17]/ I/O ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory onSA[19:0] I/O SYSTEM ADDRESS[19:0]. These bi-directional address lines define the
GPO[7:1] the ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns theselection with the granularity of 1 byte within the 1-Megabyte section of memory
ISA Bus. The LA[23:17] lines become inputs whenever an ISA master ownsdefined by the LA[23:17] address lines. The address lines SA[19:17] that are
the ISA Bus. If the EIO bus is used, these signals become a general purpose coincident with LA[19:17] are defined to have the same values as LA[19:17] for
output.all memory cycles. For I/O accesses, only SA[15:0] are used, and SA[19:16] are
During Reset: High-Z After Reset: Undefined During POS: Last LA/GPOundefined. SA[19:0] are outputs when PIIX4 owns the ISA Bus. SA[19:0] are
MEMCS16# I/O MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17]inputs when an external ISA Master owns the ISA Bus.
without any qualification of the command signal lines. ISA slaves that are During Reset: High-Z After Reset: Undefined During POS: Last SA
16-bit memory devices drive this signal low. PIIX4 ignores MEMCS16#SBHE# I/O SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a
during I/O access cycles and refresh cycles. MEMCS16# is an input whenbyte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is
PIIX4 owns the ISA Bus. PIIX4 drives this signal low during ISA master tonegated during refresh cycles. SBHE# is an output when PIIX4 owns the ISA Bus.
PCI memory cycles.SBHE# is an input when an external ISA master owns the ISA Bus.
MEMR# I/O MEMORY READ. MEMR# is the command to a memory slave that it may During Reset: High-Z After Reset: Undefined During POS: High
drive data onto the ISA data bus. MEMR# is an output when PIIX4 is a masterSD[15:0] I/O SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on
on the ISA Bus. MEMR# is an input when an ISA master, other than PIIX4,the ISA Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond
owns the ISA Bus. This signal is also driven by PIIX4 during refresh cycles. to the low order byte. SD[15:0] are undefined during refresh.
For DMA cycles, PIIX4, as a master, asserts MEMR#.During Reset: High-Z After Reset: Undefined During POS: High-Z
During Reset: High-Z After Reset: High During POS: High
SMEMR# O STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA
MEMW# I/O MEMORY WRITE. MEMW# is the command to a memory slave that it maymemory slave to drive data onto the data lines. If the access is below the 1-Mbyte
latch data from the ISA data bus. MEMW# is an output when PIIX4 owns therange (00000000h?00FFFFFh) during DMA compatible, PIIX4 master, or ISA
ISA Bus. MEMW# is an input when an ISA master, other than PIIX4, owns the .master cycles, PIIX4 asserts SMEMR#. SMEMR# is a delayed version of
ISA Bus. For DMA cycles, PIIX4, as a master, asserts MEMW#.MEMR#.
During Reset: High-Z After Reset: High During POS: High
IGNNE# OD IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore
REFRESH# I/O REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when anumeric exception pin on the CPU. IGNNE# is only used if the PIIX4
refresh cycle is in progress. It should be used to enable the SA[7:0] address to
coprocessor error reporting function is enabled. If FERR# is active, indicating a
the row address inputs of all banks of dynamic memory on the ISA Bus. Thus,
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
when MEMR# is asserted, the entire expansion bus dynamic memory isIGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If
refreshed. Memory slaves must not drive any data onto the bus during refresh.FERR# is not asserted when the Coprocessor Error Register is written, the
As an output, this signal is driven directly onto the ISA Bus. This signal is an
IGNNE# signal is not asserted.
output only when PIIX4 DMA refresh controller is a master on the bus
During Reset: High-Z After Reset: High-Z During POS: High-Z
responding to an internally generated request for refresh. As an input,
REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.INIT OD INITIALIZATION. INIT is asserted in response to any one of the following
During Reset: High-Z After Reset: High During POS: Highconditions. When the System Reset bit in the Reset Control Register is reset to 0
and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by asserting
RSTDRV O RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the INIT. PIIX4 also asserts INIT if a Shut Down Special cycle is decoded on the PCI
ISA/EIO Bus. PIIX4 asserts this signal during a hard reset and during Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h, bit 0. When
power-up. RSTDRV is asserted during power-up and negated after PWROK isasserted, INIT remains asserted for approximately 64 PCI clocks before being
driven active. RSTDRV is also driven active for a minimum of 1 ms if a hard negated. This signal is active high for Pentium processor and active-low for
reset has been programmed in the RC register.Pentium II processor as determined by CONFIG1 signal.
During Reset: High After Reset: Low During POS: Low
Pentium Processor:
During Reset: Low After Reset: Low During POS: Low
Pentium II Processor:
During Reset: High After Reset: High During POS: High
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ACEC
