61206120N N/B MAINTENANCEN N/B MAINTENANCE
3.33.3 INTEL 82371EB PCIINTEL 82371EB PCI--TOTO--ISA / IDE ISA / IDE XXCCELERATOR (PIIXELERATOR (PIIX4) (5).4) (5).
SIGNAL TYPE DESCRIPTIONSIGNAL TYPE DESCRIPTION
INTR OD CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that an SUSCLK O SUSPEND CLOCK. 32.768-kHz output clock provided to the Host-to-PCI
interrupt request is pending and needs to be serviced. It is asynchronous with bridge used for maintenance of DRAM refresh. This signal is stopped during
respect to SYSCLK or PCICLK and is always an output. The interrupt controllerSuspend-to-Disk and Soft Off modes. For values During Reset, After Reset, and
must be programmed following PCIRST# to ensure that INTR is at a known state.During POS, see the Suspend/Resume and Resume Control Signaling section.
During Reset: Low After Reset: Low During POS: Low
SYSCLK O ISA SYSTEM CLOCK. SYSCLK is the reference clock for the ISA bus. It
NMI OD NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskabledrives the ISA bus directly. The SYSCLK is generated by dividing PCICLK by
interrupt to the CPU. PIIX4 generates an NMI when either SERR# or IOCHK# is4. The SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. For PCI
asserted, depending on how the NMI Status and Control Register is programmed. accesses to the ISA bus, SYSCLK may be stretched low to synchronize BALE
The CPU detects an NMI when it detects a rising edge on NMI. After the NMIfalling to the rising edge of SYSCLK.
interrupt routine processes the interrupt, the NMI status bits in the NMI StatusDuring Reset: Running After Reset: Running During POS: Low
and Control Register are cleared by software. The NMI interrupt routine must
PDA[2:0] O PRIMARY DISK ADDRESS[2:0]. These signals indicate which byte in either
read this register to determine the source of the interrupt. The NMI is reset by
the ATA command block or control block is being addressed. If the IDE signals
setting the corresponding NMI source enable/disable bit in the NMI Status and
are configured for Primary and Secondary, these signals are connected to the
Control Register. To enable NMI interrupts, the two NMI enable/disable bits in
corresponding signals on the Primary IDE connector. If the IDE signals are
the register must be set to 0, and the NMI mask bit in the NMI Enable/Disable
configured for Primary 0 and Primary 1, these signals are used for the Primary 0
and Real Time Clock Address Register must be set to 0. Upon PCIRST#, this
connector.
signal is driven low.
During Reset: Low After Reset: Low During POS: LowPDCS1# O PRIMARY DISK CHIP SELECT FOR 1F0H- -1F7H RANGE. For ATA
command register block. If the IDE signals are configured for Primary and
SMI# OD SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous
Secondary, this output signal is connected to the corresponding signal on the
output that is asserted by PIIX4 in response to one of many enabled hardware or
Primary IDE connector. If the IDE signals are configured for Primary Master and
software events. The CPU recognizes the falling edge of SMI# as the highest .
Primary Slave, this signal is used for the Primary Master connector.
priority interrupt in the system, with the exception of INIT, CPURST, and
During Reset: High After Reset: High During POS: High
FLUSH.
During Reset: High-Z After Reset: High-Z During POS: High-ZPDCS3# O PRIMARY DISK CHIP SELECT FOR 3F0- -3F7 RANGE. For ATA control
register block. If the IDE signals are configured for Primary and Secondary, this
STPCLK# OD STOP CLOCK. STPCLK# is an active low synchronous output that is asserted
output signal is connected to the corresponding signal on the Primary IDE
by PIIX4 in response to one of many hardware or software events. STPCLK#
connector. If the IDE signals are configured for Primary Master and Primary
connects directly to the CPU and is synchronous to PCICLK.
Slave, this signal is used for the Primary Master connector.
During Reset: High-Z After Reset: High-Z During POS: High-
During Reset: High After Reset: High During POS: High
RTCX1, I/O RTC CRYSTAL INPUTS: These connected directly to a 32.768-kHz crystal.
PDD[15:0] I/O PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or
RTCX2 External capacitors are required. These clock inputs are required even if the
from the IDE device. If the IDE signals are configured for Primary and
internal RTC is not being used.
Secondary, these signals are connected to the corresponding signals on the
CLK48 I 48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller. This Primary IDE connector. If the IDE signals are configured for Primary Master
signal may be stopped during suspend modes.and Primary Slave, this signal is used for the Primary Master connector.
PCICLK I FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, SDA[2:0] O SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in
PCICLK provides timing for all transactions on the PCI Bus. All other PCIeither the ATA command block or control block is being addressed. If the IDE
signals are sampled on the rising edge of PCICLK, and all timing parameters aresignals are configured for Primary and Secondary, these signals are connected to
defined with respect to this edge. Because many of the circuits in PIIX4 run offthe corresponding signals on the Secondary IDE connector. If the IDE signals are
the PCI clock, this signal MUST be kept active, even if the PCI bus clock is not configured for Primary Master and Primary Slave, these signals are used for the
active.Primary Slave connector.
OSC I 14.31818-MHZ CLOCK. Clock signal used by the internal 8254 timer. This
clock signal may be stopped during suspend modes.
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ACEC
