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5.2 Intel ICH7-M South Bridge (1)
PCI Interface Signals PCI Interface Signals (Continued)
Signal Name Type Description Name Type Description
IRDY# I/O Initiator Ready: AD[31:0] I/O PCI Address/Data:
IRDY# indicates the ICH7's ability, as an initiator, to complete the AD[31:0] is a multiplexed address and data bus. During the first clock
current data phase of the transaction. It is used in conjunction with of a transaction, AD[31:0] contain a physical address (32 bits).
TRDY#. A data phase is completed on any clock both IRDY# and During subsequent clocks, AD[31:0] contain data. The Intel? ICH7
TRDY# are sampled asserted. During a write, IRDY# indicates the will drive all 0s on AD[31:0] during the address phase of all PCI
ICH7 has valid data present on AD[31:0]. During a read, it indicates Special Cycles.
the ICH7 is prepared to latch data. IRDY# is an input to the ICH7 C/BE[3:0]# I/O Bus Command and Byte Enables:
when the ICH7 is the target and an output from the ICH7 when the The command and byte enable signals are multiplexed on the same
ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until PCI pins. During the address phase of a transaction, C/BE[3:0]#
driven by an initiator. define the bus command. During the data phase C/BE[3:0]# define
TRDY# I/O Target Ready: the Byte Enables.
TRDY# indicates the Intel? ICH7's ability as a target to complete the C/BE[3:0]# Command Type
current data phase of the transaction. TRDY# is used in conjunction 0000b Interrupt Acknowledge
with IRDY#. A data phase is completed when both TRDY# and 0001b Special Cycle
IRDY# are sampled asserted. During a read, TRDY# indicates that 0010b I/O Read
the ICH7, as a target, has placed valid data on AD[31:0]. During a 0011b I/O Write
write, TRDY# indicates the ICH7, as a target is prepared to latch data. 0110b Memory Read
TRDY# is an input to the ICH7 when the ICH7 is the initiator and an 0111b Memory Write
output from the ICH7 when the ICH7 is a target. TRDY# is tri-stated 1010b Configuration Read
from the leading edge of PLTRST#. TRDY# remains tri-stated by the 1011b Configuration Write
ICH7 until driven by a target. 1100b Memory Read Multiple
STOP# I/O Stop: 1110b Memory Read Line
STOP# indicates that the ICH7, as a target, is requesting the initiator 1111b Memory Write and Invalidate
to stop the current transaction. STOP# causes the ICH7, as an All command encodings not shown are reserved. The ICH7 does not
initiator, to stop the current transaction. STOP# is an output when the decode reserved values, and therefore will not respond if a PCI master
ICH7 is a target and an input when the ICH7 is an initiator. generates a cycle using one of the reserved values.
PAR I/O Calculated/Checked Parity: DEVSEL# I/O Device Select:
PAR uses ?even? parity calculated on 36 bits, AD[31:0] plus The ICH7 asserts DEVSEL# to claim a PCI transaction. As an output,
C/BE[3:0]#. ?Even? parity means that the ICH7 counts the number ofthe ICH7 asserts DEVSEL# when a PCI master peripheral attempts
one within the 36 bits plus PAR and the sum is always even. The an access to an internal ICH7 address or an address destined DMI
ICH7 always calculates PAR on 36 bits regardless of the valid byte (main memory or graphics). As an input, DEVSEL# indicates the
enables. The ICH7 generates PAR for address and data phases and response to an ICH7-initiated transaction on the PCI bus. DEVSEL#
only guarantees PAR to be valid one PCI clock after the is tri-stated from the leading edge of PLTRST#. DEVSEL# remains
corresponding address or data phase. The ICH7 drives and tristates tri-stated by the ICH7 until driven by a target device.
PAR identically to the AD[31:0] lines except that the ICH7 delays FRAME# I/O Cycle Frame:
PAR by exactly one PCI clock. PAR is an output during the address The current initiator drives FRAME# to indicate the beginning and
phase (delayed one clock) for all ICH7 initiated transactions. PAR is duration of a PCI transaction. While the initiator asserts FRAME#,
an output during the data phase (delayed one clock) when the ICH7 is data transfers continue. When the initiator negates FRAME#, the
the initiator of a PCI write transaction, and when it is the target of a transaction is in the final data phase. FRAME# is an input to the
read transaction. ICH7 checks parity when it is the target of a PCI ICH7 when the ICH7 is the target, and FRAME# is an output from
write transaction. If a parity error is detected, the ICH7 will set the the ICH7 when the ICH7 is the initiator. FRAME# remains tristated
appropriate internal status bits, and has the option to generate an by the ICH7 until driven by an initiator.
NMI# or SMI#.
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