75217521Plus / N N/B MAINTENANCEPlus / N N/B MAINTENANCE
1.2.15 SiS900 Fast Ethernet PCI Bus 10/100Mbps LAN Single Chip with OnNow
Support
SiS900 is a single chip 10/100Mbps Fast Ethernet LAN solution, which fully integrates both the Media Access
Controller (MAC) with PCI bus master interface and 802.3u compliant 10/100Mbps physical layer interface into a 128
pins PQFP, 0.35um process chip. It is targeted at low-cost, low-power, high volume desktop PC motherboards, mobile
PC module, adapter cards, and embedded systems.
SiS900 fully implements the PCI bus version 2.1 interface for host communications. Packet descriptors and data are
transferred via bus-mastering DMA channels, reducing the burden on the host CPU. The buffer management scheme
utilized by SiS900 optimizes the use of memory space and the system bus. Descriptor information, describing the buffer
space in which packet information is held, is symmetrical between transmit and receive operations. SiS900 supports
both half-duplex and full-duplex operations with minimum inter frame gap and IEEE802.3x full-duplex flow control. In
order to meet the PC 98 and the Green PC power saving requirements, SiS900 supports ACPI and Network Device
Class Power Management specification. All the device states of D0, D1, D2, D3hot, and D3cold are implemented.
SiS900 also supports Remote Wake On LAN and OnNow for the Desktop PC management. Additional features include
a serial EEPROM interface for device information access and a Boot ROM interface up to 128K bytes for remote boot
functions support.
SiS900 also integrates analog interface for twisted pair Fast Ethernet applications. SiS900 can be configured for either
100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation. SiS900 consists of 4B5B/Manchester
encoder/decoder, scrambler/descrambler, 100Base-TX/10Base-T twisted pair transmitter with wave shaping and output
driver, 100Base-TX/10Base-T twisted pair receiver with on chip equalizer and baseline wander correction, clock and
data recovery, and Auto Negotiation capability. The addition of internal output wave shaping circuitry and on-chip
filters eliminates the need for external filters normally required in 100Base-TX and 10Base-T applications. SiS900 can
automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip Auto Negotiation
algorithm. SiS900 PHY can access eleven 16-bit registers through the internal Management Interface (MI) serial port.
These registers contain configuration inputs, status outputs, and device capabilities.
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