75217521Plus / N N/B MAINTENANCEPlus / N N/B MAINTENANCE
5. Pin Descriptions Of Major Components
5.1 Pentium III/Celeron FC-PGA2 CPU
Alphabetical Signal Reference
PWRGOOD Relationship at Power On
Signal NameI/OSignal DescriptionThe PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
PICCLKIThe PICCLK (APIC Clock) signal is an input clock to the processoragainst voltage sequencing issues. The PWRGOOD signal should be driven high throughout boundary
2.5Vand system logic or I/O APIC that is required for operation of thescan operation.
Tolerantprocessor, system logic, and I/O APIC components on the APIC bus.
Signal NameI/OSignal Description
PICD[1:0]I/OThe PICD[1:0] (APIC Data) signals are used for bi-directional serial
REQ[4:0]#I/OThe REQ[4:0]# (Request Command) signals must be connected to the
1.5Vmessage passing on the APIC bus. They must be connected to theGTL+appropriate pins/balls on both agents on the system bus. They are
Tolerantappropriate pins/balls of all APIC bus agents, including the processor
asserted by the current bus owner when it drives A[35:3]# to define
Open-and the system logic or I/O APIC components. If the PICD0 signal is
drainsampled low on the active-to-inactive transition of the RESET#the currently active transaction type.
RESET#IAsserting the RESET# signal resets the processor to a known state
signal, then the APIC is hardware disabled.
GTL+and invalidates the L1 and L2 caches without writing back Modified
PLL1, PLL2Analog The PLL1 and PLL2 signals provide isolated analog decoupling is(M state) lines. For a power-on type reset, RESET# must stay active
required for the internal PLL. See Section 3.2.2 for a description of
for at least 1 msec after Vcc and BCLK have reached their proper DC
the analog decoupling circuit.
PRDY#OThe PRDY# (Probe Ready) signal is a processor output used byand AC specifications and after PWRGOOD has been asserted. When
observing active RESET#, all bus agents will deassert their outputs
GTL+debug tools to determine processor debug readiness.
within two clocks. RESET# is the only GTL+ signal that does
PREQ#IThe PREQ# (Probe Request) signal is used by debug tools to requestnot have on-die GTL+ termination. A 56.2e1% terminating resistor
1.5Vdebug operation of the processor.
connected to VccT is required.
Tolerant
A number of bus signals are sampled at the active-to-inactive
PWRGOODIPWRGOOD (Power Good) is a 2.5-V tolerant input. The processortransition of RESET# for the power-on configuration. The
2.5Vrequires this signal to be a clean indication that clocks and the power
configuration options are described in Section 4 and in the Pentium II
Tolerantsupplies (Vcc, VccT, etc.) are stable and within their specifications.
Clean implies that the signal will remain low, (capable of sinkingProcessor Developer?s Manual.
Unless its outputs are tri-stated during power-on configuration, after
leakage current) and without glitches, from the time that the power
an active-to-inactive transition of RESET#, the processor optionally
supplies are turned on, until they come within specification. Theexecutes its built-in self-test (BIST) and begins program execution at
signal will then transition monotonically to a high (2.5V) state. Figure
reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected
26 illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and powerto the appropriate pins/balls on both agents on the system bus.
RP#I/OThe RP# (Request Parity) signal is driven by the request initiator and
must again be stable before the rising edge of PWRGOOD. It must
GTL+provides parity protection on ADS# and REQ[4:0]#. RP# should be
also meet the minimum pulse width specified in Table 17 (Sectionconnected to the appropriate pins/balls on both agents on the system
3.7) and be followed by a 1 ms RESET# pulse.
bus.
A correct parity signal is high if an even number of covered signals
PWRGOOD Relationship at Power Onare low and low if an odd number of covered signals are low. This
definition allows parity to be high when all covered signals are high.
RS[2:0]#IThe RS[2:0]# (Response Status) signals are driven by the response
GTL+agent (the agent responsible for completion of the current transaction)
and must be connected to the appropriate pins/balls on both agents on
the system bus.
87 |
ACEC
