SECTION 2
CIRCUIT DESCRIPTION
2-1. LOGIC CIRCUIT DESCRIPTIONWide band data signal is applied to the audio signal processor via
FMDEM terminal, and is converted into the logic level signal at
The functional block diagram is shown in LOGIC CIRCUITthe comparator. Then the signal goes to the digital processor
BLOCK DIAGRAM.(KE5A220 or KE5A221) and acquires bit synchronization at the
The logic circuit consists of the following parts.digital phase locked loop circuit. Next, the signal is converted into
non-return zero signal from Manchester code at the integrated and
Y MPU (including Digital processor)dump circuit. From this signal Barker code (11100010010) is de-
Y EEPROM, 32 kbitstected at the word synchronizing detection circuit, and then the
Y FEEPROM, 128 kbytesinformation and parity bit signal (40 bits) is cleaned up by a 3/5
Y Audio signal processormajority vote circuit.
Y Power supply IC
Y LCD driver (Interface Board)From the signal, syndrome is detected at the syndrome detector,
Y 20-digit dot matrix liquid crystal display (Interface Board)and an interrupt is requested on the MPU to inform the reception
of the signal. When an interrupt occurs the software of the MPU
The audio from the microphone is amplified at the microphoneallows 28 information bits and 12 parity bits to enter the MPU by
amplifier, goes through the analog switch and transmit audio isway of data bus. The software checks syndrome at first, then will
input at the transmit-audio terminal. The analog sdo errwitch can beor correction, if there are any.
turned off with Command 5100 (Change-path) of the test set when
the characteristics of transmit audio of the radio unit is measured.2-2. RADIO CIRCUIT DESCRIPTION
The audio is compressed at the compressor. The compr2-2-1. General Descriptionessor out-
put does through the band pass filter, pre-emphasis, deviation lim-
iter, and post-deviation filter, and is added with the contrThe functional blocol signalk diagram is shown in the radio circuit block
at the audio signal processor. The summed signal is adiagram.pplied to the
modulation input terminal of the radio portion.
Signals received from the cell site pass through the duplexer to the
The demodulated signal from the receiver goes through the de-receiver circuit, where they are amplified and demodulated. The
emphasis circuit in the audio signal processor, the band pass freceived signals may be vilteroice and/or coded signaling informa-
and the expander, and is added at the summing ampliftion. Frier with theom the receiver circuit, voice signals and coded signaling
tone signal. The summed signal is applied to the rinformation are sent to the logic circuit.eceive audio
terminal.
To transmit signals, the Transmitter carrier is frequency-modula-
Analog SW, Compressor and expander is in the Audio signal prtion with voice and/or coded signaling inforo-mation. The carrier is
cessor.then passed through a duplexer to the antenna.
For wideband data transmission, the data signal is f2-2-2.irst encoded Synthesizer Circuit
into the BCH code with the software for the MPU. The BCH code
is sent via the 8-bit data bus to digital processor (KE5A220 orThe equipment has two phase-locked-loop frequency synthesizer.
KE5A221). The parallel data bus is converted to serOne is used to produce the RF modulatorial data to the. Another one is used to
32-bit shift register of digital signal is sent to the audio signalproduce the RF signals for 1st local oscillator injections of the
processor.receiver.
In the audio signal processor, the Manchester code signal goesThe synthesizer of 1st local and TX local oscillator (U306) con-
through analog switch, variable resistor T.DATA trols an RF signal, between 941 MHz and 966 MHz, or 824 MHz,VR5 (variable
from +1.6 to �1.4 dB in 0.2 dB steps), the 4th order loand 849 MHz according to a DC control vw pass filteroltage. The internal dual
with 20 kHz cut-off frequency and lastly TX VR3 (vmodules prescaler diariable fromvides the signal from the buffer amplifier by
�2.5 dB to �15.2 dB in 0.1 dB steps), and then appears at the128 or 129. The output of a portion of the programmable divider
FMMOD terminal.function determines whether 128 or 129 is a divider. Channel as-
signment numbers are determined by a 18 bit serial data input se-
Supervisory audio tones (SAT: 6030 Hz, 6000 Hz, 5970 Hz) arequence from the logic circuit.
demodulated at the radio portion and appears at the FMDEM ter-
minal. The SAT signal is then applied to the logic portion. The phase detector comparThees the phases of the two signals from
SAT signal goes through the band pass filter hathe diving the 6-kHzviders and drivers the charge pump according to the com-
center frequency in the audio signal processor, and is conparison result. If the loop goes out of lock, the phase detector gen-verted to
logic level signal through the comparator. The loerates an unlock detect signal.gic level signal is
phase-synchronized at the digital phase locked loop in digital pro-
cessor. The comparator output goes through SAT daTta rhe cemarharge pump translates the digital output of the phase detec-k and,
the low pass filter, TSAT VR6 (variable from �9.6 to �14.1 dB intor into a current source or sink (depending on the phase informa-
0.3 dB steps), analog switch in the audio signal prtion). ocessorThe lo. Tw-pass fhere-ilter integrates this change in correct to pro-
after, the SAT signal takes the same signal processing rduce the DC voute as theoltage that controls the VCO (U305 and U404) out-
wide band data signal.put frequency.
Dual Tone Multipul-Frequency signal is generated aThe 14.4 MHz t the audioTCXO (U307) output is divided by 960 to produce
signal processor, and the signal is converted into sine wthe 15.0 kHz rave. eTfhenerence frequency for the synthesizer.
the sine wave signal is passed through DTMF VR10. After that,
the signal takes the same signal processing route as voice.
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ACEC
SONY
