Initial reset
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU.
The CPU then initializes its internal circuit and clears data in the working strage RAM.
Power ON reset
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU first raises
APO signal to +5V to generat DVDD voltage, then raises RESET signal to +5V. During this period the
gate array, the DSP and the key touch LSI initializes their internal circuit.
CPU (HD6433298A18P)
The 16-bit CPU contains a 32k-bit ROM, a 1k-bit RAM, seven 8-bit I/O ports, an A/D convertor and serial
interfaces. The CPU accesses to the working strage RAM, the DSP and the key touch LSI. The CPU also
controls buttons, LEDs, bender input and MIDI input/output.
Pin No. TerminalIn/OutFunction
1P40Out KO signal data output
2P41Out Clock for KO signal data
3P42Out APO (Auto Power Off) signal output. ON: High, OFF: Low
4P43Out Read enable signal output
5P44Out Write enable signal output
6P45 Not used.
7P46Out 10MHz clock output
8P47In Wait signal input. Connected to +5V.
9TXDOut MIDI signal output
10RXDIn MIDI signal input
11P52Out Reset signal output
12-RESETIn Reset signal input
13-NMIIn Power ON signal input.
14VCCIn +5V source
15-STBYIn Standby signal input. Connected to +5V.
16VSSIn Ground (0V) source
17XTALIn 20MHz clock input
18EXTALIn 20MHz clock input
19, 20 MD1, MD0In Mode selection input. (Internal ROM mode --- MD1: Hight, MD0: Low)
21AVSSIn Ground (0V) source for internal DAC
22AN0In Analog input. Connected to the bender volume.
23 ~ 29 P71 ~ P77In Button input signal input
30AVCCIn +5V source for internal DAC
31 ~ 38 P60 ~ P67Out LED segment signal output
39VCCIn +5V source
40 ~ 56 P27 ~ P10Out Address bus
48VSSIn Ground (0V) source
57 ~ 64 P30 ~ P37 Ijn/Out Data bus
N 6 N |
ACEC
PANASONIC
