Pin No.TerminalIn/OutFunction
1 ~ 8CD0 ~ CD7In/Out Data bus
9, 10CE1, TRSBNNot used
11GND7InGround (0 V) source
12CK16OutTerminal for 24.576 MHz clock check point
13VCC6In+5 V source
14CK0InClock input. Connected to terminal CK16.
15TCKBNNot used
16VCC1In+5 V source
17GND1InGround (0 V) source
18, 19XT0, XT1In/Out 24.576 MHz clock input/output
20SGLInSystem control terminal. Single chip system: Open
21CCSBInChip select signal input
22 ~ 25CA0 ~ CA3In Address bus
26CE0InNot used. Connected to ground.
27CWRBInWrite enable signal
28CRDBInRead enable signal
29 ~ 32NNNot used
33RESBInReset signal input
34TESBInNot used. Connected to +5 V.
35 ~ 39NNNot used
40 ~ 49
52 ~ 57RD0 ~ RD15InData bus for the sound source ROM
50VCC2In+5 V source
51GND2InGround (0 V) source
58RA23OutNot used
59RA22OutChip select signal for the sound source ROM
60RA21OutNot used
61 ~ 73
75 ~ 82RA0 ~ RA20OutAddress bus for the sound source ROM
74GND5InGround (0 V) source
83WOK2OutNot used
84VCC3In+5 V source
85GND3InGround (0 V) source
86WOK1OutWord clock for the DAC
87SOLMOutNot used
88SOLPOutSerial sound data output
89BOKOutBit clock output
90 ~ 92NNNot used
93VCC5In+5 V source
94, 95
97 ~ 105EA0 ~ EA14OutAddress bus for the effect RAM
107, 109
110, 112
96EWEBOutWrite enable signal for the effect RAM
N 8 N |
ACEC
PANASONIC
