2. Generation of VCC Voltage
Fig. 3-3 shows the VCC voltage generation circuit block diagram.
(1) Operation when the operating mode is switched from STOP mode (SLEEP state) to PLAY mode
When either the PLAY key of the Discman or the PLAY key or the FF key or the REW key of the remote control is premessed, the syst
controller IC801 outputs the "L" signal fr@? [PCON]. om pinWhen "L" is output, Q415 and Q412 are turned on by this "L" signal so that
the input to pin2 [CTL] of the SWITCHING REGULATOR IC401 is set to "L" to start the SWITCHING REGULATOR IC401. As the
SWITCHING REGULATOR IC401 starts, the internal oscillator of IC401 starts oscillating so that the PWM wdaveform that is generate
by the PWM comparator inside IC401, is output from pin5 [OUT] of the SWITCHING REGULATOR IC401. As the PWM waveform
is output from pin5 [OUT] of IC401, Q402 and Q401 start the switching operation which starts up the STEP-UP/DOWN DC-DC
CONVERTER that generates 2.75 V. The switching output from Q401 is smoothed out by L401 and C403,e- and is divided by the voltag
divider resistors of R401, RV401, and R402. The output voltage from the volta1ge-di [IN] of IC401.vider resistors is fed back to pin
Based on this feedback voltage, IC401 controls the duty ratio of the PWM waveform that is generated by the PWM comparatorrder, in o
to control the output voltage, then to generate the VCC voltage (2.75 V).
(2) Operation when the operating mode is switched from PLAY mode to STOP mode (SLEEP state)
When either the STOP key of the Discman or that of the remote control is pressed, the system controller IC801 outputs the "H" signal
from pin@? [PCON]. Q412 is turned off by this "H" signal which stops the SWITCHING REGULATOR IC401, and stops outputting the
VCC voltage 2.75 V. Note that when the RESUME function is turned off, the system controller IC801 motheves the optical pickup to
innermost circumference, and sets the output fr@? [PCON] to "H". om pin When the RESUME function is turned on, the optical pickup
is not moved to the innermost circumference.
The waveform timing chart during generation of the VCC voltage is shown in Fig. 3-4.
� 2.8 V
1 Q402
GATE0_
2 Q401� 3.2 V
COLLECTOR0_
3 Q401� 3 V
BASE0_
4 TP401� -5 V
VCC� 2.75 V
0_
Fig. 3-4 Waveform timing chart during generation of the VCC voltage
N 30 N |
ACEC
SONY
