CIRCUIT DESCRIPTION
1) Receiver System
The receiver system is the double superheterodyne.
The first IF is 21.4MHz andthe second IF is 455kHz.
1. Front EndThe signal from the antenna is passed through a low-pass fitter and input to
the RF coil L4.
The signal trom L4 is amplified by Q1 and led to the band passtilter (L5, L6,
L7), and led to the first mixer gate of Q2.
2. First MixerThe amplified signal (fo) by Q1 is mixed with the first local oscillator signal
(fo -21.4MHz) from the PLL circuit by the first-stage mixer Q2 and so is
converted into the first IF signal.
The unwanted frequency band of the first IF signal is eliminated by the
monolithic crystal filter (XF1), and led to IF amplifier Q3.
3. IF AmplifierThe first IF signal is amplified by Q3, and inputto pin16 of IC1, where it is
mixed with the second local oscillator signal (21.855MHz) and so is con-
verted into the second IF signal (455kHz).
The second lF signal is output from pin3 of IC1, and unwanted frequency
band of the second lF signal is eliminated by a ceramic filter (FL1).
The resulting signal is then amplified by the second lF limiting amplifier, and
detected by quadrature circuit. The audio signal is output from ping of IC1.
4. Audio CircuitThe detected signal from IC1 is passed through the low-pass filter and led to
the flat amplifier Q13. When the optional Tone Squelch unit is equipped, the
tone signal is eliminated by lC701.
Q13 is switched ON/OFF by AFC slgnal from CPU.
The audio signal is input to the main volume (VR3) and amplified by the
power amplifier IC3 to drive the speaker.
The power supply voltage of IC3 is limited by AF regulator consisting of Q14
and Q15 to prevent the speaker from overdriving. The power supply voltage
of IC3 is switched ON/OFF by AFP signal.
5. Squelch Circuit The noise in the audio signal from IC1 is passed through the squelch control
variable resistor (VR4) and input to pin10 of IC1. The audio signal is ampli-
fied by filter amplifier of IC1 and output to pin11. The desired noise of the
audio signal is eliminated by the high-pass filter and amplified by Q12. The
resulting signal is rectified by D13 and then input to pin12 of IC1. When the
squelch circuit is close, pin13 of ICl goes to "low". When the squelch circuit
is open or a signal is received, pin13 goes to "high", then the signal of pin13
is led to CPU.
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