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5. Pin Descriptions of Major Components
5.4 PC Card Interface controller
16-Bit PC Card Interface Control (Slots A and B) CardBus PC Card Interface System (Slots A and B)
TERMINAL TERMINAL
NO. NO.
NAME SLOT A? SLOT B? I/O DESCRIPTION NAME SLOT A?SLOT B?I/O DESCRIPTION
PDV GHK PDV GHK PDV GHK PDV GHK
WE 110 R19 46 P3 O Write enable. WE is used to strobe memory write CCLK 112 P18 48 P6 O CardBus clock. CCLK provides synchronous
data into 16-bit memory PC Cards. WE is also timing for all transactions on the CardBus
used for memory PC Cards that employ interface. All signals except CRST, CCLKRUN,
programmable memory technologies. CINT, CSTSCHG, CAUDIO, CCD2, CCD1,
DMA terminal count. WE is used as TC during CVS2, and CVS1 are sampled on the rising edge
DMA operations to a 16-bit PC Card that of CCLK, and all timing parameters are defined
supports DMA. The PCI1420 asserts WE to with the rising edge of this signal. CCLK
indicate TC for a DMA read operation. operates at the PCI bus clock frequency, but it
WP(IOIS16) 139 H18 73 U9 I Write protect. WP applies to 16-bit memory PC can be stopped in the low state or slowed down
Cards. WP reflects the status of the write-protect for power savings.
switch on 16-bit memory PC Cards. For 16-bit CCLKRUN 139 H18 73 U9 O CardBus clock run. CCLKRUN is used by a
I/O cards, WP is used for the 16-bit port CardBus PC Card to request an increase in the
(IOIS16) function. CCLK frequency, and by the PCI1420 to indicate
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC that the CCLK frequency is going to be
Cards. IOIS16 is asserted by the 16-bit PC Carddecreased.
when the address on the bus corresponds to an CRST 124 L18 58 W5 I/O CardBus reset. CRST brings CardBus PC
address to which the 16-bit PC Card responds, Card-specific registers, sequencers, and signals
and the I/O port that is addressed is capable of to a known state. When CRST is asserted, all
16-bit accesses. CardBus PC Card signals are placed in a
DMA request. WP can be used as the DMA high-impedance state, and the PCI1420 drives
request signal during DMA operations to a 16-bitthese signals to a valid logic level. Assertion can
PC Card that supports DMA. If used, then the PC be asynchronous to CCLK, but deassertion must
Card asserts WP to indicate a request for a DMA be synchronous to CCLK.
operation. ? Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18
VS1 134 J18 68 U8 I/O Voltage sense 1 and voltage sense 2. VS1 and are A_CCLK.
VS2 122 M19 56 P7 VS2, when used in conjunction with each other, ? Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6
determine the operating voltage of the PC Card. are B_CCLK.
? Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19
are A_WE.
? Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3
are B_WE.
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ACEC
