MITAC 7321 Repair Manual

7321 N/B Maintenance7321 N/B Maintenance
5. Pin Descriptions of Major Components
5.4 PC Card Interface controller
16-Bit PC Card Interface Control (Slots A and B)
TERMINAL TERMINAL
NO. NO.
NAME SLOT A? SLOT B? I/O DESCRIPTION NAME SLOT A?SLOT B?I/O DESCRIPTION
PDV GHK PDV GHK PDV GHK PDV GHK
IORD 99 W15 33 L5 O I/O read. IORD is asserted by the PCI1420 to READY 135J1769V8I Ready. The ready function is provided by
enable 16-bit I/O PC Card data output during (IREQ) READY when the 16-bit PC Card and the host
host I/O read cycles. socket are configured for the memory-only
DMA write. IORD is used as the DMA write interface. READY is driven low by the 16-bit
strobe during DMA operations from a 16-bit PC memory PC Cards to indicate that the memory
Card that supports DMA. The PCI1420 asserts card circuits are busy processing a previous
IORD during DMA transfers from the PC Card write command. READY is driven high when the
to host memory. 16-bit memory PC Card is ready to accept a new
IOWR 101 V15 35 M2 O I/O write. IOWR is driven low by the PCI1420 to data transfer command.
strobe write data into 16-bit I/O PC Cards during Interrupt request. IREQ is asserted by a 16-bit
host I/O write cycles. I/O PC Card to indicate to the host that a device
DMA read. IOWR is used as the DMA write on the 16-bit I /O PC Card requires service by the
strobe during DMA operations from a 16-bit PC host software. IREQ is high (deasserted) when no
Card that supports DMA. The PCI1420 asserts interrupt is requested.
IOWR during transfers from host memory to the REG 130K1763P8O Attribute memory select. REG remains high for
PC Card. all common memory accesses. When REG
? Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14is asserted, access is limited to attribute memory
are A_INPACK. (OE or WE active) and to the I/O space (IORD or
? Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 IOWR active). Attribute memory is a separately
are B_INPACK. accessed section of card memory and is generally
used to record card capacity and other
configuration and attribute information.
TERMINAL DMA acknowledge. REG is used as a DMA
NO. acknowledge (DACK) during DMA operations
I/O DESCRIPTION
NAME SLOT A? SLOT B? to a 16-bit PC Card that supports DMA. The
PDV GHK PDV GHK PCI1420 asserts REG to indicate a DMA
OE 98 U14 32 L6 O Output enable. OE is driven low by the PCI1420 operation. REG is used in conjunction with the
to enable 16-bit memory PC Card data output DMA read (IOWR) or DMA write (IORD)
during host memory read cycles. strobes to transfer data.
DMA terminal count. OE is used as terminal RESET 124L1858W5O PC Card reset. RESET forces a hard reset to a
count (TC) during DMA operations to a 16-bit 16-bit PC Card.
PC Card that supports DMA. The PCI1420 WAIT 136J1470W8I Bus cycle wait. WAIT is driven by a 16-bit PC
asserts OE to indicate TC for a DMA write Card to extend the completion of the memory or
operation. I/O cycle in progress.

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