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5.2 Intel ICH6-M South Bridge(7)
Processor Interface Signals Processor Interface Signals (Continued)
Name Type Description Name Type Description
A20M# O Mask A20: A20M# will go active based on either setting the NMI O Non-Maskable Interrupt: NMI is used to force a non-Maskable
appropriate bit in the Port 92h register, or based on the A20GATE interrupt to the processor. The ICH6 can generate an NMI when
input being active. either SERR# is asserted or IOCHK# goes active via the SERIRQ#
CPUSLP# O Processor Sleep: This signal puts the processor into a state that saves stream. The processor detects an NMI when it detects a rising edge on
substantial power compared to Stop-Grant state. However, during that NMI. NMI is reset by setting the corresponding NMI source
time, no snoops occur. enable/disable bit in the NMI Status and Control register (I/O
The Intel? ICH6 can optionally assert the CPUSLP# signal when Register 61h).
going to the S1 state, and will always assert it when going to C3 or SMI# O System Management Interrupt: SMI# is an active low output
C4. synchronous to PCICLK. It is asserted by the ICH6 in response to one
FERR# I Numeric Coprocessor Error: This signal is tied to the coprocessor of many enabled hardware or software events.
error signal on the processor. FERR# is only used if the ICH6 STPCLK# O Stop Clock Request: STPCLK# is an active low output synchronous
coprocessor error reporting function is enabled in the OIC.CEN to PCICLK. It is asserted by the ICH6 in response to one of many
register (Chipset ConfigurationRegisters:Offset 31FFh: bit 1). If hardware or software events.
FERR# is asserted, the ICH6 generates an internal IRQ13 to its When the processor samples STPCLK# asserted, it responds by
interrupt controller unit. It is also used to gate the IGNNE# signal to stopping its internal clock.
ensure that IGNNE# is not asserted to the processor unless FERR# is RCIN# I Keyboard Controller Reset CPU: The keyboard controller can
active. FERR# requires an external weak pull-up to ensure a high generate INIT# to the processor. This saves the external OR gate with
level when the coprocessor error function is disabled. the ICH6?s other sources of INIT#. When the ICH6 detects the
NOTE: FERR# can be used in some states for notification by the assertion of this signal, INIT# is generated for 16 PCI clocks.
processor of pending interrupt events. This functionality is NOTE: The ICH6 will ignore RCIN# assertion during transitions to
independent of the OIC register bit setting. the S1, S3, S4, and S5 states.
IGNNE# O Ignore Numeric Error: This signal is connected to the ignore error A20GATE I A20 Gate: A20GATE is from the keyboard controller. The signal
pin on the processor. IGNNE# is only used if the ICH6 coprocessor acts as an alternative method to force the A20M# signal active. It
error reporting function is enabled in the OIC.CEN register (Chipset saves the external OR gate needed with various other chipsets.
Configuration Registers:Offset 31FFh: bit 1). If FERR# is active, CPUPWRGD / OD Processor Power Good: This signal should be connected to the
indicating a coprocessor error, a write to the Coprocessor Error GPO[49] O processor?s PWRGOOD input to indicate when the processor power
register (I/O register F0h) causes the IGNNE# to be asserted. is valid. This is an open- drain output signal (external pull-up resistor
IGNNE# remains asserted until FERR# is negated. If FERR# is not required) that represents a logical AND of the ICH6?s PWROK and
asserted when the Coprocessor Error register is written, the IGNNE# VRMPWRGD signals.
signal is not asserted. This signal may optionally be configured as a GPO.
INIT# O Initialization: INIT# is asserted by the ICH6 for 16 PCI clocks to
reset the processor.
ICH6 can be configured to support processor Built In Self Test
(BIST).
INIT3_3V# O Initialization 3.3 V: This is the identical 3.3 V copy of INIT#
intended for Firmware Hub.
INTR O Processor Interrupt: INTR is asserted by the ICH6 to signal the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
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