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5.2 Intel ICH6-M South Bridge(6)
Power Management Interface Signals Power Management Interface Signals (Continued)
Name Type Description Name Type Description
PWRBTN# I Power Button: The Power Button will cause SMI# or SCI to indicate PLTRST# O Platform Reset: The ICH6 asserts PLTRST# to reset devices on the
a system request to go to a sleep state. If the system is already in a platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The
sleep state, this signal will cause a wake event. If PWRBTN# is ICH6 asserts PLTRST# during power-up and when S/W initiates a
pressed for more than 4 seconds, this will cause an unconditional hard reset sequence through the Reset Control register (I/O Register
transition (power button override) to the S5 state. Override will occur CF9h). The ICH6 drives PLTRST# inactive a minimum of 1 ms after
even if the system is in the S1-S4 states. This signal has an internal both PWROK and VRMPWRGD are driven high. The ICH6 drives
pull-up resistor and has an internal 16 ms de-bounce on the input. PLTRST# active a minimum of 1 ms when initiated through the Reset
RI# I Ring Indicate: This signal is an input from a modem. It can be Control register (I/O Register CF9h).
enabled as a wake event, and this is preserved across power failures. NOTE: PLTRST# is in the VccSus3_3 well.
SYS_RESET# I System Reset: This pin forces an internal reset after being debounced. THRM# I Thermal Alarm: This is an active low signal generated by external
The ICH6 will reset immediately if the SMBus is idle; otherwise, it hardware to generate an SMI# or SCI.
will wait up to 25 ms ? 2 ms for the SMBus to idle before forcing a THRMTRIP# I Thermal Trip: When low, this signal indicates that a thermal trip
reset on the system. from the processor occurred, and the ICH6 will immediately
RSMRST# I Resume Well Reset: This signal is used for resetting the resume transition to a S5 state. The ICH6 will not wait for the processor stop
power plane logic. grant cycle since the processor has overheated.
LAN_RST# I LAN Reset: When asserted, the internal LAN controller will be put SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. This signal
into reset. This signal must be asserted for at least 10 ms after the shuts off power to all non-critical systems when in S3 (Suspend To
resume well power (VccSus3_3 and VccSus1_5) is valid. When RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.
de-asserted, this signal is an indication that the resume well power is SLP_S4# O S4 Sleep Control: SLP_S4# is for power plane control. This signal
stable. shuts power to all non-critical systems when in the S4 (Suspend to
NOTE: LAN_RST# must de-assert at some point to complete ICH6 Disk) or S5 (Soft Off) state.
power up sequencing. NOTE: This pin must be used to control the DRAM power in order
WAKE# I PCI Express* Wake Event: Sideband wake signal on PCI Express to use the ICH6?s DRAM power-cycling feature. Refer to Chapter
asserted by components requesting wakeup. 5.14.10.2 for details.
MCH_SYNC# I MCH SYNC: This input is internally ANDed with the PWROK SLP_S5# O S5 Sleep Control: SLP_S5# is for power plane control. This signal is
input. used to shut power off to all non-critical systems when in the S5 (Soft
Connected to the ICH_SYNC# output of (G)MCH. Off) states.
SUS_STAT# / O Suspend Status: This signal is asserted by the ICH6 to indicate that PWROK I Power OK: When asserted, PWROK is an indication to the ICH6
LPCPD# the system will be entering a low power state soon. This can be that core power has been stable for at least 99 ms and PCICLK has
monitored by devices with memory that need to switch from normal been stable for at least 1 mS. An exception to this rule is if the system
refresh to suspend refresh mode. It can also be used by other is in S3 HOT , in which PWROK may or may notstay asserted even
peripherals as an indication that they should isolate their outputs that though PCICLK may be inactive. PWROK can be driven
may be going to powered-off planes. This signal is called LPCPD# onasynchronously. When PWROK is negated, the ICH6 asserts
the LPC I/F. PLTRST#.
SUSCLK O Suspend Clock: This clock is an output of the RTC generator circuit NOTE: PWROK must de-assert for a minimum of three RTC clock
to use by other chips for refresh clock. periods in order for the ICH6 to fully reset the power and properly
VRMPWRGD I VRM Power Good: This should be connected to be the processor?s generate the PLTRST# output
VRM Power Good signifying the VRM is stable. This signal is
internally ANDed with the PWROK input.
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