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while operating at PCI click rates up to 33 MHz. Several low-power modes enable the host power management system
to further reduce power consumption.
The CP1410 supports the following features:
- ability to wake from D3hot and D3cold
- 144-Pin Low-Profile QFP (PGE), 144-ball MicroStar Ball Grid Array (GGU) package, or 209-Pin MicroStar Ball
Grid Array (GHK) package
- 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
- mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
- Single PC Card or CardBus slots with hot insertion and removal
- burst transfers to maximize data throughput on the PCI bus and CardBus Cards
- Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI interrupts, and
serial ISA IRQ and PCI interrupts
- Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
- Pipelined architecture allows greater than 130M bps throughput from CardBus-to-PCI and from PCI-to-CardBus
- Interface to parallel single-slot PC Card power interface switches like the TI TPS2211
- Up to five general-purpose I/Os
- Programmable output select for CLKRUN
- Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
- Two I/O windows and two memory windows available to each CardBus socket
- Exchangeable Card Architecture (ExCA) compatible registers are mapped in memory and I/O space
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