8640 8640 N/B MN/B Maaintenanceintenance
5.3 SIS 962(MuTIOL? Media I/O south bridge )
Keyboard Control Interface MAC Interface Continue
Name Pin Attr Signal Description Name Pin Attr Signal Description
KBDAT / I/OD Keyboard Dada: TXEN O Transmit Enable:
GPIO15 O/OD When the internal keyboard controller is enabled, this pin is 3.3V -AUX When set to a 1, and the transmit state machine is idle, then the
3.3V/5V -AUX used as the keyboard data signal. transmit state machine becomes active. This bit will read back
KBCLK / I/OD Keyboard Clock: as a 1 whenever the transmit state machine is active. After initial
GPIO16 O/OD When the internal keyboard controller is enabled, this pin is power-up, software must insure that the transmitter has
3.3V/5V -AUX used as the keyboard clock signal. completely reset before setting this bit
PMDAT / I/OD PS2 Mouse Data: MDIO I/O Management Data I/O:
GPIO17 O/OD When the internal keyboard and PS2 mouse controllers are 3.3V/5V -AUX Bi-direction signal used to transfer management information for
3.3V/5V -AUX enabled, this pin is used as PS2 mouse data signal. the external physical unit. Requires external pull-up resistor.
PMCLK / I/OD PS2 Mouse Clock: RXDV I Receive Data Valid.
GPIO18 O/OD When the internal keyboard and PS2 mouse controllers are 3.3V/5V -AUX This indicates that the external physical unit is presenting
3.3V/5V -AUX enabled, this pin is used as the PS2 mouse clock signal. recovered and decoded nibbles on the RXD[3:0] and that
RXCLK is synchronous to the recovered data. This signal will
encompass the frame, starting with the Start-Of-Frame delimiter
and excluding the End-Of-Frame delimiter.
COL I Collision Detect:
3.3V/5V -AUX This signal is asserted high asynchronous by the external
MAC Interface physical unit upon detection of a collision on the medium. It?ll
Name Pin Attr Signal Description remain asserted as long as the collision condition persists.
RXER I RX Packet Error CRS I Carrier Sense:
3.3V/5V -AUX This event is signaled after the last received descriptor in a 3.3V/5V -AUX This signal is asserted high asynchronously by the physical unit
failed packet reception that has been updated with valid status. upon detection of a non-idle medium.
MIICLK25M I PHY 25MHz Clock Input: RXCLK I Receive Clock
3.3V/5V -AUX This pin provides the 25MHz clock signal input to the built-in 3.3V/5V -AUX A continuous clock that is recovered from the incoming data.
oscillator. During 100Mb/s operation RXCLK is 25MHz and during
MDC O Management Data Clock: 10Mb/s this is 2.5MHz.
3.3V -AUX Clock signal with a maximum rate of 2.5MHz used to transfer TXCLK I Transmit Clock
management data for the external physical unit on the 3.3V/5V -AUXA continuous clock that is sourced by the physical unit. During
MIIMDIO pin. 100Mb/s operation RXCLK is 25MHz and during 10Mb/s this
TXD[0:3] I Receive Data: is 2.5MHz.
3.3V/5V -AUX This is a group of 4 data signals aligned on nibble boundaries
which are driven synchronous to the RXCLK by the external
physical unit.
TXEN O Transmit Data:
3.3V -AUX This is a group of 4 data signals which are driven synchronous
to the TXCLK for transmission to the external physical unit.
RXD[0:3] I Receive Data:
3.3V/5V -AUX This is a group of 4 data signals aligned on nibble boundaries
which are driven synchronous to the RXCLK by the external
physical unit.
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