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5.3 Intel ICH7-M South Bridge (3)
Serial ATA Interface Signals (Continued) Platform LAN Connect Interface Signals
Name Type Description Name Type Description
SATA3GP/ I Serial ATA 3 General Purpose: LAN_CLK I LAN I/F Clock:
GPIO37 Same function as SATA0GP, except for SATA Port 3. This signal is driven by the Platform LAN Connect component. The
If interlock switches are not required, this pin can be configured as frequency range is 5 MHz to 50 MHz.
GPIO37. LAN_RXD[2:0]I Received Data:
SATALED# OC Serial ATA LED: The Platform LAN Connect component uses these signals to transfer
This is an open-collector output pin driven during SATA command data and control information to the integrated LAN controller. These
activity. It is to be connected to external circuitry that can provide the signals have integrated weak pull-up resistors.
current to drive a platform LED. When active, the LED is on. When LAN_TXD[2:0]O Transmit Data:
tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is The integrated LAN controller uses these signals to transfer data and
required. control information to the Platform LAN Connect component.
NOTE: An internal pull-up is enabled only during PLTRST# LAN_RSTSYNCO LAN Reset/Sync:
assertion. The Platform LAN Connect component?s Reset and Sync signals are
SATACLKREQOD Serial ATA Clock Request: multiplexed onto this pin.
#/GPIO35 (Native)/This is an open-drain output pin when configured as
I/O (GP)SATACLKREQ#. It is to connect to the system clock chip. When
active, request for SATA Clock running is asserted. When tri-stated,
it tells the Clock Chip that SATA Clock can be stopped. An external
pull-up resistor is required.
Other Clock
Name Type Description
CLK14 I Oscillator Clock:
This clock is used for 8254 timers. It runs at 14.31818 MHz. This
Serial Peripheral Interface (SPI) Signals clock is permitted to stop during S3 (or lower) states.
Name Type Description CLK48 I 48 MHz Clock:
This clock is used to run the USB controller. Runs at 48.000 MHz.
SPI_CS# I/O SPI Chip Select:
This clock is permitted to stop during S3 (or lower) states.
Also used as the SPI bus request signal.
SATA_CLKP I 100 MHz Differential Clock:
SPI_MISO I SPI Master IN Slave OUT:
SATA_CLKN These signals are used to run the SATA controller at 100 MHz. This
Data input pin for Intel? ICH7.
clock is permitted to stop during S3/S4/S5 states.
SPI_MOSI O SPI Master OUT Slave IN:
DMI_CLKP, I 100 MHz Differential Clock:
Data output pin for ICH7.
DMI_CLKN These signals are used to run the Direct Media Interface. Runs at 100
SPI _ARB I SPI Arbitration:
MHz.
SPI arbitration signal is used to arbitrate the SPI bus with Intel PRO
82573E Gigabit Ethernet Controller when Shared Flash is
implemented.
SPI_CLK O SPI Clock:
SPI clock signal, during idle the bus owner will drive the clock signal
low. 17.86 MHz.
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