EN 2169.DVDR70 & DVDR75/0x1Circuit-,nICndescriptionsnandnlistnofnabbreviations
Pin Connections and Functions
Pin #NameDescription
Power Supply Connections (not shown on Block diagram)
See list VGround connections. Connect to the digital ground plane. Pins: 2, 17, 34, 55, 64, 74, 85,
SS
96, 106, 115, 124, 132, 138, 145, 152, 159, 168
See list VPad Ring digital power connections. Connect to the digital 3.3 volt power supply and
DD33
decouple to the digital ground plane. Pins: 1, 33, 63, 73, 84, 95, 105, 114, 123, 137, 144,
151, 167
See list VCore Logic digital power connections. Connect to the digital 2.5 volt power supply and
DD25
decouple to the digital ground plane. Pins: 16, 54, 107, 158
43AVGround connection for the clock PLL circuits. Connect to the digital ground plane
SS
42AVAnalog power connections for the clock PLL circuit. Connect to a separately decoupled 2.5
DD
volt power supply and decouple directly to the AV pin..
SS
Control Signals
49RESETBReset. When this input is set low it will reset all the internal registers to the default states.
Refer to the section on the control registers for details of these states. The device must be
reset after it is powered-up.
53OEWhen this pin is set high the outputs of the FLI2200 will be enabled; when it is set low the
outputs will be set into a high-impedance state.
56-58IFORMATInput signal format control. The settings of these pins set the format of the input signal.
2-0
This can be overridden by the IFmtOvr bit, bit 3 in register 00, allowing this function to be
H
2
set or changed via the IC bus. Please refer to the description of register 00 for details.
H
59-61OFORMAT2-0Output signal format control. The settings of these pins set the format of the output signal.
This can be overridden by the OFmtOvr bit, bit 3 in register 07, allowing this function to be
H
2
set or changed via the IC bus. Please refer to the description of register 07 for details.
H
44-45DADDRThe settings of DADDR allow the device address of the control bus to be programmed to
1-01-0
prevent conflict with the other devices connected to the bus. DADDR allow the device
1-0
address to be set to any of the following values: C0/C1, C2/C3, E0/E1, E2/E3. Please refer
HHHH
to the section ?Control Bus Operation and Protocol? for further information.
46MODEWhen this pin is set low the control bus will operate in the slave mode; allowing the device to
programmed from an external controller. When it is set high the FLI2200 will self-program from
2
an external IC memory connected to the bus. Please refer to the ?Control Bus Operation and
Control Protocol? section for more details.
47SDA2-wire serial control bus data. Data can be written to the control registers via this pin when it
is in the input mode and data can be read from the status registers when it is in the output
mode. Refer to the section on the serial port for timing and format details and to the section on
the registers for programming information.
48SCL2-wire serial control bus clock. When the control port operates in slave mode this pin will be
an input and when it operates in the self programming mode it will be an output.
40PIXCLKPixel clock input. This clock is used to drive all the circuits in the FLI2200. An internal PLL is
used to upconvert this clock to provide the master clock signal and other clocks used
internally. Note that when the FLI2200 is used in the D1 input mode the PIXCLK input
should run at the rate of two cycles per pixel (one for luma and one for chroma).
62N/P/IN/OUT NTSC/PAL input or output. The default function of this pin is NTSC/PAL signal indicator
output. When the input video signal is a 525 line signal this pin will be set high and when it
is a 625 line signal the pin is set low. This function of this pin can be programmed to be an
input according to the setting of this pin if the NPOp bits, bits 5-4 in register 03, are set
1-0H
to 00, overriding the internal line counter. i.e., it will treat the signal as a 525 line signal
H
when it is set high and a 625 line signal when it is set low. |
ACEC
