BD-V3501, BD-V3510
BD-V3511
AD8323ARU (MAIN ASSY : IC1701)
Y UP Stream Amplifier
" Block Diagram
VCC
BYP
5,9,10,19,20,23,27
21
R1
AD8323
15
VIN+VOUT+
DIFF OR
SINGLEBUFFERATTENUATIONPOWER
AMP
INPUTCORE14
VIN�AMPVOUT�
ZOUT DIFF =
8
75
R2DECODE
ZIN (SINGLE) = 8008POWER-DOWN
ZIN (DIFF) = 1.6kLOGIC
DATA LATCH
8
SHIFT
REGISTER
1234,8,11,12,13,16,67
DATENDATA CLK17,18,22,24,28PDSLEEP
GND
" Pin Function
PIN FUNCTION DESCRIPTIONS
Pin No.MnemonicDescription
1DATENData Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
2SDATASerial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first.
3CLKClock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
4, 8, 11,12,GNDCommon External Ground Reference.
13, 16, 17, 18,
22, 24, 28
5, 9, 10, 19,CC VCommon Positive External Supply Voltage. A 0.1 F capacitor must decouple each pin.
20, 23, 27
6PDLogic O0� powers down the part. Logic O1� powers up the part.
7Low Power Sleep Mode. In the Sleep mode, the AD8323Os supply current is reduced to 4 mA. A
SLEEP
Logic O0� powers down the part (High ZOUT State) and a Logic O1� powers up the part.
14OUT �Negative Output Signal.
15OUT+Positive Output Signal.
21BYPInternal Bypass. This pin must be externally ac-coupled (0.1 F cap).
25VIN+Noninverting Input. DC-biased to approximately VCC /2. For single-ended inverting operation,
use a 0.1 F decoupling capacitor and a 39.2 resistor between VIN+ and ground.
26VIN�Inverting Input. DC-biased to approximately VCC /2. Should be ac-coupled with a 0.1 F capacitor.
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ACEC
