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5. Pin Descriptions of Major Components
5.1 Intel 915GM North Bridge(1)
Host Interface Signals Host Interface Signals (Continued)
Signal Name Type Description Signal Name Type Description
HADS# I/O Host Address Strobe: HDRDY# I/O Host Data Ready:
AGTL+ The system bus owner asserts HADS# to indicate the first of two AGTL+Asserted for each cycle that data is transferred.
cycles of a request phase. The GMCH can also assert this signal for HA[31:3]# I/O Host Address Bus:
snoop cycles and interrupt messages. AGTL+ HA[31:3]# connects to the CPU address bus. During processor cycles
HBNR# I/O Host Block Next Request: 2X the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during
AGTL+ Used to block the current request bus owner from issuing a new snoop cycles on behalf of DMI.
request. This signal is used to dynamically control the CPU bus
HA[31:3]# are transferred at 2x rate.
pipeline depth. Note that the address is inverted on the CPU bus.
HBPRI# O Host Bus Priority Request: HADSTB[1:0]#I/O Host Address Strobe:
AGTL+ The GMCH is the only Priority Agent on the system bus. It asserts AGTL+HA[31:3]# connects to the CPU address bus. During CPU cycles, the
this signal to obtain the ownership of the address bus. This signal has 2X source synchronous strobes are used to transfer HA[31:3]# and
priority over symmetric bus requests and will cause the current HREQ[4:0]# at the 2x transfer rate.
symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted. Strobe Address Bits
HBREQ0# I/O Host Bus Request 0#: HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#
AGTL+ The GMCH pulls the processor bus HBREQ0# signal low during HD[63:0]# I/O Host Data:
HCPURST#. The signal is sampled by the processor on the AGTL+These signals are connected to the CPU data bus. HD[63:0]# are
active-to-inactive transition of HCPURST#. 4X transferred at 4x rate.
HBREQ0# should be tri-stated after the hold time requirement has
been satisfied. Note that the data signals are inverted on the CPU bus depending on
HCPURST# O Host CPU Reset: the HDINV[3:0]# signals.
AGTL+ The CPURST# pin is an output from the GMCH. The GMCH asserts HDSTBP[3:0]# I/O Host Differential Host Data Strobes:
HCPURST# while RSTIN# is asserted and for approximately 1 ms HDSTBN[3:0]#AGTL+The differential source synchronous strobes are used to transfer
4X HD[63:0]# and HDINV[3:0]# at the 4x transfer rate.
after RSTIN# is deasserted. HCPURST# allows the processor to Strobe Data Bits
begin execution in a known state.
HDBSY# I/O Host Data Bus Busy: HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, HDINV[3]#
AGTL+ Used by the data bus owner to hold the data bus for transfers HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, HDINV[2]#
requiring more than one cycle. HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, HDINV[1]#
HDEFER# O Host Defer: HDSTBP[0]#, HDSTBN[0]# HD[15:00]#, HDINV[0]#
AGTL+ Signals that the GMCH will terminate the transaction currently being HHIT# I/O Host Hit:
snooped with either a deferred response or with a retry response. AGTL+Indicates that a caching agent holds an unmodified version of the
HDINV[3:0]# I/O Host Dynamic Bus Inversion: requested line.
AGTL+ Driven along with the HFD[63:0]# signals. Indicates if the associated Also, driven in conjunction with HITM# by the target to extend the
signals are inverted or not. HDINVF[3:0]# are asserted such that the snoop window.
number of data bits driven electrically low (low voltage) within the HHITM# I/O Host Hit Modified:
corresponding 16-bit group never exceeds 8. AGTL+Indicates that a caching agent holds a modified version of the
HDINV# Data Bits requested line and that this agent assumes responsibility for providing
HDINV[3]# HD[63:48]# the line.
HDINV[2]# HD[47:32]# Also, driven in conjunction with HIT# to extend the snoop window.
HDINV[1]# HD[31:16]#
HDINV[0]# HD[15:0]#
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