80X0DX N/B Maintenance
5.2 Intel ICH6-M South Bridge(9)
AC ?97/Intel ? High Definition Audio Link Signals Power and Ground Signals
Name Type Description Name Description
ACZ_RST# O AC ?97/Intel ? High Definition Audio Reset: Master hardware reset Vcc3_3 3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3,
to external codec(s). S4, S5 or G3 states.
ACZ_SYNC O AC ?97/Intel High Definition Audio Sync: 48 kHz fixed rate sample Vcc1_5_A 1.5 V supply for core well logic, group A (52 pins). This power may be shut off in
sync to the codec(s). Also used to encode the stream number. S3, S4, S5 or G3 states.
ACZ_BIT_CLK I/O AC ?97 Bit Clock Input: 12.288 MHz serial data clock generated by Vcc1_5_B 1.5 V supply for core well logic, group B (45 pins). This power may be shut off in
the external codec(s). This signal has an integrated pull-down resistor S3, S4, S5 or G3 states.
(see Note below). Vcc2_5 2.5V supply for internal logic (2 pins). This power may be shut off in S3, S4, S5 or
Intel High Definition Audio Bit Clock Output: 24.000 MHz serial G3 states.
data clock generated by the Intel? High Definition Audio controller NOTE: This voltage may be generated internally (see Section 2.22.1 for strapping
(the Intel ICH6). Thissignal has an integrated pull-down resistor so option). If generated internally, these pins should not be connected to an external
that ACZ_BIT_CLK does not float when an supply.
Intel High Definition Audio codec (or no codec) is connected but the V5REF Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut
signals are temporarily configured as AC ?97. off in S3, S4, S5 or G3 states.
ACZ_SDOUT O AC ?97/Intel High Definition Audio Serial Data Out: Serial TDM VccSus3_3 3.3 V supply for resume well I/O buffers (20 pins). This power is not expected to
data output to the codec(s). This serial output is double-pumped for a be shut off unless the system is unplugged.
bit rate of 48 Mb/s for Intel High Definition Audio. VccSus1_5 1.5 V supply for resume well logic (3 pin). This power is not expected to be shut
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a off unless the system is unplugged.
functional strap. See Section 2.22.1 for more details. There is a weak This voltage may be generated internally (see Section 2.22.1 for strapping option).
integrated pull-down resistor on the ACZ_SDOUT pin. If generated internally, these pins should not be connected to an external supply.
ACZ_SDIN[2:0] I AC ?97/Intel High Definition Audio Serial Data In [2:0]: Serial V5REF_Sus Reference for 5 V tolerance on resume well inputs (1 pin). This power is not
TDM data inputs from the three codecs. The serial input is expected to be shut off unless the system is unplugged.
single-pumped for a bit rate of 24 Mb/s for Intel High Definition VccRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This
Audio. These signals have integrated pull-down resistors, which are power is not expected to be shut off unless the RTC battery is removed or
always enabled. completely drained.
NOTES: NOTE: Implementations should not attempt to clear CMOS by using a jumper to
1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for pull VccRTC low. Clearing CMOS in an ICH6-based platform can be done by
details. using a jumper on RTCRST# or GPI.
2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This VccUSBPLL 1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This
bit selects the mode of the shared Intel High Definition Audio/AC ?97 signals. When set to 0 power may be shut off in S3, S4, S5 or G3 states. This signal must be powered
AC ?97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit even if USB not used.
defaults to 0 (AC ?97 mode). 1.5 V supply for core well logic (1 pins). This signal is used for the DMI PLL. This
VccDMIPLL
power may be shut off in S3, S4, S5 or G3 states.
VccSATAPLL 1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL.
Firmware Hub Interface Signals This power may be shut off in S3, S4, S5 or G3 states. This signal must be
Name Type Description powered even if SATA not used.
V_CPU_IO Powered by the same supply as the processor I/O voltage (3 pins). This supply is
FWH[3:0] / I/O Firmware Hub Signals. These signals are multiplexed with the LPC
used to drive the processor interface signals listed in Table 2-13.
LAD[3:0] address signals.
Vss Grounds (172 pins).
FWH[4] / O Firmware Hub Signals. This signal is multiplexed with the LPC
LFRAME# LFRAME# signal.
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