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5.1 Intel Pentium 4 Processor mPGA478 Socket
Name Type Description Name Type Description
BPM[5:0]# Input/ BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance D[63:0]# Input/ D[63:0]# (Data) are the data signals. These signals provide a 64-bit
Output monitor signals. They are outputs from the processor which indicate the Outputdata path between the processor system bus agents, and must
status of breakpoints and programmable counters used for monitoring connect the appropriate pins on all such agents. The data driver
processor performance. BPM[5:0]# should connect the appropriate pins asserts DRDY# to indicate a valid data transfer.
of all Pentium 4 processor in the 478-pin package system bus agents. D[63:0]# are quad-pumped signals and will thus be driven four
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. times in a common clock period. D[63:0]# are latched off the falling
PRDY# is a processor output used by debug tools to determine edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
processor debug readiness. data signals correspond to a pair of one DSTBP# and one DSTBN#.
BPM5# provides PREQ# (Probe Request) functionality for the TAP The following table shows the grouping of data signals to data
port. PREQ# is used by debug tools to request debug operation of the strobes and DBI#.
processor. Please refer to the Intel? Pentium? 4 Processor in the Quad-Pumped Signal Groups
478-pin Package and Intel? 850 Chipset Platform Design Guide for
more detailed information. DSTBN#/
Data Group DBI#
These signals do not have on-die termination. Refer to the Intel? DSTBP#
Pentium? 4 Processor in the 478-pin Package and Intel? 850 D[15:0]# 0 0
Chipset Platform Design Guide for termination requirements. D[31:16]# 1 1
BPRI# Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the D[47:32]# 2 2
processor system bus. It must connect the appropriate pins of all D[63:48]# 3 3
processor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new requests, Furthermore, the DBI# pins determine the polarity of the data
unless such requests are part of an ongoing locked operation. The signals. Each group of 16 data signals corresponds to one DBI#
priority agent keeps BPRI# asserted until all of its signal. When the DBI# signal is active, the corresponding data
requests are completed, then releases the bus by deasserting BPRI#. group is inverted and therefore sampled active high.
BR0# Input/ BR0# drives the BREQ0# signal in the system and is used by the DBI[3:0]# Input/ DBI[3:0]# are source synchronous and indicate the polarity of the
Output processor to request the bus. During power-on configuration this pin is OutputD[63:0]# signals. The DBI[3:0]# signals are activated when the data
sampled to determine the agent ID = 0. on the data bus is inverted. The bus agent will invert the data bus
This signal does not have on-die termination and must be signals if more than half the bits, within the covered group, would
terminated. change level in the next cycle.
Output The BCLK[1:0] frequency select signals BSEL[1:0] are used to select DBI[3:0] Assignment To Data Bus
the processor input clock frequency. The required frequency is
determined by the processor, chipset and clock synthesizer. All agents
BSEL[1:0] Bus Signal Data Bus Signals
must operate at the same frequency. The Pentium 4 processor in the
478-pin package operates currently at a 400 MHz system bus frequency DBI3# D[63:48]#
(100 MHz BCLK[1:0] frequency). DBI2# D[47:32]#
COMP[1:0] Analog COMP[1:0] must be terminated on the system board using precision DBI1# D[31:16]#
resistors. Refer to the Intel? Pentium? 4 Processor in the 478-pin DBI0# D[15:0]#
Package and Intel? 850 Chipset Platform Design Guide for details on
implementation. DBR# Output DBR# is used only in processor systems where no debug port is
implemented on the system board. DBR# is used by a debug port
interposer so that an in-target probe can drive system reset. If a
debug port is implemented in the system, DBR# is a no connect in
the system. DBR# is not a processor signal.
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