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5.2 Intel ICH7-M South Bridge (2)
PCI Interface Signals (Continued) Serial ATA Interface Signals
Signal Name Type Description Name Type Description
PERR# I/O Parity Error: SATA0TXP O Serial ATA 0 Differential Transmit Pair:
An external PCI device drives PERR# when it receives data that has a SATA0TXN These are outbound high-speed differential signals to Port 0.
parity error. The ICH7 drives PERR# when it detects a parity error. SATA0RXP I Serial ATA 0 Differential Receive Pair:
The ICH7 can either generate an NMI# or SMI# upon detecting a SATA0RXN These are inbound high-speed differential signals from Port 0.
parity error (either detected internally or reported via the PERR#
SATA1TXP O Serial ATA 1 Differential Transmit Pair:
signal).
SATA1TXN These are outbound high-speed differential signals to Port 1.
REQ[0:3]# I PCI Requests:
SATA1RXP I Serial ATA 1 Differential Receive Pair:
REQ[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The REQ[4]# and
SATA1RXN These are inbound high-speed differential signals from Port 1.
GPIO22 REQ5# pins can instead be used as a GPIO.
SATA2TXP O Serial ATA 2 Differential Transmit Pair:
REQ[5]#/GPIO1
SATA2TXN These are outbound high-speed differential signals to Port 2.
GNT[0:3]# O PCI Grants:
SATA2RXP I Serial ATA 2 Differential Receive Pair:
GNT[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The GNT4# and
SATA2RXN These are inbound high-speed differential signals from Port 2.
GPIO48 GNT5# pins can instead be used as a GPIO. Pull-up resistors are not
SATA3TXP O Serial ATA 3 Differential Transmit Pair:
GNT[5]#/ required on these signals. If pull-ups are used, they should be tied to
SATA3TXN These are outbound high-speed differential signals to Port 3.
GPIO17# the Vcc3_3 power rail. GNT5#/GPIO17 has an internal pull-up.
SATA3RXP I Serial ATA 3 Differential Receive Pair:
PCICLK I NOTE: PCI Clock:
SATA3RXN These are inbound high-speed differential signals from Port 3.
This is a 33 MHz clock. PCICLK provides timing for all transactions
on the PCI Bus. SATARBIAS O Serial ATA Resistor Bias:
PCIRST# O PCI Reset: These are analog connection points for an external resistor to ground.
This is the Secondary PCI Bus reset signal. It is a logical OR of the SATARBIAS# I Serial ATA Resistor Bias Complement:
primary interface PLTRST# signal and the state of the Secondary Bus These are analog connection points for an external resistor to ground.
Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). SATA0GP/ I Serial ATA 0 General Purpose:
PLOCK# I/O PCI Lock: GPIO21 This is an input pin which can be configured as an interlock switch
This signal indicates an exclusive bus operation and may require corresponding to SATA Port 0. When used as an interlock switch
multiple transactions to complete. The ICH7 asserts PLOCK# when it status indication, this signal should be drive to ?0? to indicate that the
performs non-exclusive transactions on the PCI bus. PLOCK# is switch is closed and to ?1? to indicate that the switch is open.
ignored when PCI masters are granted the bus in desktop If interlock switches are not required, this pin can be configured as
configurations. GPIO21.
SERR# I/OD System Error: SATA1GP/ I Serial ATA 1 General Purpose:
SERR# can be pulsed active by any PCI device that detects a system GPIO19 Same function as SATA0GP, except for SATA Port 1.
error condition. Upon sampling SERR# active, the ICH7 has the If interlock switches are not required, this pin can be configured as
ability to generate an NMI, SMI#, or interrupt. GPIO19.
PME# I/OD PCI Power Management Event: SATA2GP/ I Serial ATA 2 General Purpose:
PCI peripherals drive PME# to wake the system from low-power GPIO36 Same function as SATA0GP, except for SATA Port 2.
states S1-S5. PME# assertion can also be enabled to generate an SCI If interlock switches are not required, this pin can be configured as
from the S0 state. In some cases the ICH7 may drive PME# active
GPIO36.
due to an internal wake event. The ICH7 will not drive PME# high,
but it will be pulled up to VccSus3_3 by an internal pull-up resistor.
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