8666 N/B Maintenance8666 N/B Maintenance
5.3 VT8235CE South Bridge - 5
UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (Continued)
Signal Name Pin # I/O Signal Description Signal Name Pin # I/O Signal Description
PDRDY Y22 I EIDE Mode: Primary I/O Channel Ready. Device ready PDDACK# Y24 O Primary Device DMA Acknowledge. Primary channel DMA
/PDDMARDY indicator UltraDMA Mode: Primary Device DMA Ready. acknowledge
/PDSTROBE Output flow control. The device mayassert DDMARDY to pause SDDACK# AD23 O Secondary Device DMA Acknowledge. Secondary channel DMA
output transfers Primary Device Strobe. Input data strobe (both acknowledge
edges). The device may stop DSTROBE to pause input data IRQ14 AD24 I Primary Channel Interrupt Request.
transfers
SDRDY AF17 I EIDE Mode: Secondary I/O Channel Ready. Device ready IRQ15 AE26 I Secondary Channel Interrupt Request.
PDCS1# V22 O Primary Master Chip Select. This signal corresponds to CS1FX#
/SDDMARDY indicator UltraDMA Mode: Secondary Device DMA Ready.
/SDSTROBE Output flow control. The devicemay assert DDMARDY to pause on the primary IDE connector.
output transfers Secondary Device Strobe. Input data strobe (both PDCS3# V23 O Primary Slave Chip Select. This signal corresponds to CS3FX# on
edges). The device may stop DSTROBE to pause input data the primary IDE connector.
transfers SDCS1# / strap AF25 O Secondary Master Chip Select. This signal corresponds to
PDIOR# W26 O EIDE Mode: Primary Device I/O Read. Device read strobe CS17X# on the secondary IDE connector. Strap low (resistor to
/PHDMARDY UltraDMA Mode: Primary Host DMA Ready. Primary channel ground) to enable serial EEPROM interface via the MII bus (this
/PHSTROBE input flow control. Thehost may assert HDMARDY to pause input disables the EExx pins). This pin has an internal pullup to default to
transfers Primary Host Strobe. Output data strobe (both edges). serial EEPROM interface via the EExx pins.
The host may stop HSTROBE to pause output data transfers SDCS3# / strap AF26 O Secondary Slave Chip Select. This signal corresponds to CS37X#
SDIOR# AF23 O EIDE Mode: Secondary Device I/O Read. Device read strobe on the secondary IDE connector. Strap information is
/SHDMARDY UltraDMA Mode: Secondary Host DMA Ready. Input flow communicated to the north bridge via VD[7].
/SHSTROBE control. The host mayassert HDMARDY to pause input transfers PDA[2-0] W24, O Primary Disk Address. PDA[2:0] are used to indicate which byte
Host Strobe B. Output strobe (both edges). The host may stop V25, in either the ATA command block or control block is being
HSTROBE to pause output data transfers W23 accessed.
PDIOW# Y25 O EIDE Mode: Primary Device I/O Write. Device write strobe SDA[2-0] / strap AE24, O Secondary Disk Address. SDA[2:0] are used to indicate which
/PSTOP UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the AC22, byte in either the ATA command block or control block is being
host prior to initiation of AF24 accessed. Strap information is communicated to the north bridge via
an UltraDMA burst; negated by the host before data is transferred inVD[6:4].
an UltraDMA burst. Assertion of STOP by the host during or after PDD[15-0] (see pin IO Primary Disk Data.
data transfer in UltraDMA mode signals the termination of the list)
burst. SDD[15-0] (see pin IO Secondary Disk Data.
SDIOW# AE23 O EIDE Mode: Secondary Device I/O Write. Device write strobe list)
/SSTOP UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the
host prior to initiation of an UltraDMA burst; negated by the host
before data is transferred in an UltraDMA burst. Assertion of STOP
by the host during or after data transfer in UltraDMA mode signals
the termination of the burst. Serial IRQ
PDDRQ Y23 I Primary Device DMA Request. Primary channel DMA request Signal Name Pin # I/O Signal Description
SDDRQ AD17 I Secondary Device DMA Request. Secondary channel DMA
SERIRQ AD9 I Serial IRQ. This pin has an internal pull-up resistor.
request
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