8666 N/B Maintenance8666 N/B Maintenance
5.2 PN800 North Bridge - 4
AGP 8x / 4x Bus Interface (Continued) AGP 8x / 4x Bus Interface (Continued)
Signal Name Pin # I/O Signal Description Signal Name Pin # I/O Signal Description
GSBA[7:0]# AE1, I Side Band Address. Provides an additional bus to pass address GWBF (GWBF# AB2 I Write Buffer Full.
(GSBA[7:0] for AE4, and command information from the master (graphics controller) for 4x)
4x) AE3, to the target (North Bridge). GRBF (GRBF# AE7 I Read Buffer Full. Indicates if the master (graphics controller)
AE2, These pins are ignored until enabled. for 4x) is ready to accept previously requested low priority read data.
AD2, When GRBF# is asserted,
AC3, the North Bridge will not return low priority read data to the
AC4, graphics controller.
AC1 GREQ (GREQ# AD4 I Request. Master (graphics controller) request for use of the
GSBSTBF AD3 I Side Band Strobe. Driven by the master to provide timing for for 4x) AGP bus.
(GSBSTB for GSBA[7:0]. 8x mode uses GSBSTBF (?First? strobe) and GGNT (GGNT# AD5 O Grant. Permission is given to the master (graphics controller) to
4x), GSBSTBS AD1 GSBSTBS (?Second? strobe). These signals are interpreted as for 4x) use the AGP bus.
(GSBSTB# for GSBSTB & GSBSTB# for AGP4x. GSERR AN1 IO System Error.
4x) (GSERR# for 4x)
GST[2:0] AE6, O Status (AGP only). Provides information from the arbiter to a GSTOP AM3 IO Stop. Asserted by the target to request the master to stop the
AE5, master to indicate what it may do. Only valid while GGNT# is (GSTOP# for 4x)current transaction. Interpreted as active high for AGP 8x.
AD6 asserted. Note: I/O pads for all pins on this page are powered by VCC15AGP. Input voltage levels are
000 Indicates that previously requested low priority read or referenced to AGPVREF.
flush data Note: The AGP interface pins can be optionally configured as additional interfaces for
is being returned to the master (graphics controller). connecting to external display devices. For simplification of the AGP pin description tables
001 Indicates that previously requested high priority read data is above and on the next page, that multiplexing is not shown here (see ?Additional I2C
being Interfaces? and ?Digital Display? pin description tables later in this document for more
returned to the master. information).
010 Indicates that the master is to provide low priority write Note: I/O pads for all pins on this page are powered by VCC15AGP. Input voltage levels are
data for a referenced to AGPVREF.
previously enqueued write command.
Note: The AGP interface pins can be optionally configured as additional interfaces for
011 Indicates that the master is to provide high priority write connecting to external display devices. For simplification of the AGP pin description tables
data for a above and on the next page, that multiplexing is not shown here (see ?Additional I2C
previously enqueued write command. Interfaces? and ?Digital Display? pin description tables later in this document for more
100 Reserved. (arbiter must not issue, may be defined in the information).
future). Note: Separate system interrupts are not provided for AGP. The AGP connector provides
101 Reserved. (arbiter must not issue, may be defined in the interrupts via PCI bus INTA-B#.
future). Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses)
110 Reserved. (arbiter must not issue, may be defined in the
Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE#
future). (to send addresses multiplexed on the AD lines) and the GSBA port (to send addresses
111 Indicates that the master (graphics controller) has been unmultiplexed). AGP masters implement one or the other or select one at initialization time
given (they are not allowed to change during runtime). Only one of the two will be used; the signals
permission to start a bus transaction. The master may enqueueassociated with the other will not be used. GRBF# has an internal pullup to maintain it in the
AGP requests by asserting GPIPE# or start a PCI transaction byde-asserted state in case it is not implemented on the master device. AGP 8x mode allows only
asserting GFRAME#. GST[2:0] are always outputs from the GSBA (GPIPE# isn?t used in 8x mode).
target (North Bridge) and inputs to the master (graphics Note: AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level
controller). when inactive resulting in no current flow.
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